GCIXP1200GB Intel, GCIXP1200GB Datasheet - Page 34

• Manufacturer Part Number: GCIXP1200GB
• Description: IC MPU NETWORK 200MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GB

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839428

Intel
34
Table 14. IX Bus Interface Pins (Continued)
®
IXP1200 Network Processor
FAST_RX2
RDYCTL#[4]/
FC_EN1#/
RXPEN#
RDYCTL#[3:0]
RDYBUS[7:0]
SOP/SOP_RX
IX Bus Signal
Names
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AJ10
AK6
AL6
AJ7
AH8
AK7
AL9
AK9
AJ9
AL8
AK8
AH9
AJ8
AL7
AH12
Pin #
I1
I1/O4/
TS
I1/O4/
TS
I1/O4/
TS
I1/O4
Type
1
1
4
8
1
Total
Ready Input from Fast Port 1 (i.e., Gigabit port). Pulldown through
10 KOhms to VSS if not used.
In 64-bit Bidirectional IX Bus Mode:
In 32-bit Unidirectional Mode:
Bidirectional Ready Control signals.
In 64-bit Bidirectional IX Bus Mode:
In 32-bit Unidirectional Mode:
8-Bit Bidirectional Ready Bus data.
Start of Packet indication.
• 1-2 MAC mode: Used as an active low flow control enable for
• 3+ MAC mode: Used in conjunction with RDYCTL#[3:0].
• In a shared IX Bus system the IXP1200 Ready Bus Master
• 1-2 MAC mode: Used as an active low flow control enable for
• 3+ MAC mode: Used as an active low enable for an external
• 1-2 MAC mode: Bits [3:0] are used to enable the transmit or
• 3+ MAC mode: The transmit and receive FIFO Ready, the
• In a shared IX Bus system the IXP1200 Ready Bus Master
• 1-2 MAC mode: Bits [3:0] are used to enable the transmit or
• 3+ MAC mode: The transmit and receive FIFO ready and flow
• Inputs the Transmit and Receive Ready Flags from IX Bus
• Outputs flow control data to IX Bus devices.
• Data bus for interprocessor communications.
• Receive Start of Packet Input in 32-bit unidirectional IX Bus
• Input/Output in 64-bit bidirectional IX Bus mode.
• In a shared IX Bus system, this pin will be tri-stated when
MAC 1 (GPIO[0]/FC_EN0#/TXPEN is used as a flow control
enable for MAC 0).
drives this pin. IXP1200 Ready Bus slave devices snoop this
pin.
MAC 1. GPIO[0]/FC_EN0#/TXPEN is used as a flow control
enable for MAC 0.
decoder for the PORTCTL[1:0] signals.
receive FIFO Ready Flags.
flow control, and inter-processor communication enables are
decoded from RDYCTL#[4:0].
drives this bus. IXP1200 Ready Bus slave devices snoop
these pins as inputs.
receive FIFO Ready Flags.
control enables are decoded from RDYCTL#[3:0].
devices.
mode.
SOP/SOP_RX is Transmit Start of Packet output according to
values programmed in the TFIFO control field. Is Receive
Start of Packet input during receive cycles.
passing ownership of the IX Bus.
Pin Descriptions
Datasheet