MPC8560CPX667JC Freescale Semiconductor, MPC8560CPX667JC Datasheet

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... MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office. © Freescale Semiconductor, Inc., 2008. All rights reserved. MPC8560EC Rev. 4.2, 1/2008 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8 3 ...

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... Figure 1. MPC8560 Block Diagram Figure 1 shows the major 256KB L2-Cache/ SRAM e500 Core Cache D Cache Core Complex Bus RapidIO-8 RapidIO Controller 16 Gb/s PCI 64b PCI Controller 133 MHz DMA Controller 10/100/1000 MAC MII, GMII, TBI, RTBI, RGMIIs 10/100/1000 MAC Freescale Semiconductor ...

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... ISDN primary rate – Freescale interchip digital link (IDL) – General circuit interface (GCI) — User-defined interfaces — Eight independent baud rate generators (BRGs) — Four general-purpose 16-bit timers or two 32-bit timers MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Overview 3 ...

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... Four banks of memory supported, each Gbyte — DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports — Full ECC support — Page mode support ( simultaneous open pages) MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 4 Freescale Semiconductor ...

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... Four global high resolution timers/counters that can generate interrupts — Supports 22 other internal interrupt sources — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Overview 5 ...

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... Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models — 9.6-Kbyte jumbo frame support — RMON statistics support — 2-Kbyte internal transmit and receive FIFOs MPC8560 Integrated Processor Hardware Specifications, Rev. 4 addressing mode 2 C interface Freescale Semiconductor ...

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... Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O — Supports power saving modes: doze, nap, and sleep — Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Overview 7 ...

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... For devices rated at 667 and 833 MHz MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 8 Table 1. Absolute Maximum Ratings Symbol V DD For devices rated at 1 GHz AV DD For devices rated at 1 GHz 1 Max Value Unit Notes V — –0.3 to 1.32 –0.3 to 1.43 V — –0.3 to 1.32 –0.3 to 1.43 Freescale Semiconductor ...

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... Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach 10 percent of theirs. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Symbol GV DD ...

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... C, and JTAG signals DD Table 2 Recommended Symbol Unit Value V DD 1.2 V ± 1.3 V ± 1.2 V ± 1.3 V ± 2.5 V ± 125 3.3 V ± 165 mV DD 2.5 V ± 125 mV OV 3.3 V ± 165 GND GND to GV REF DD/2 LV GND GND 105 j Freescale Semiconductor °C ...

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... I/O supply voltage. OV circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally supplied appropriate for the SSTL2 electrical signaling standard. DD MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor + 20 GND Not to Exceed 10 ...

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... MPC8560 Integrated Processor Hardware Specifications, Rev. 4 (Min) +7 (Max (Max) 62.5 ns +3.6 V –3.5 V Table 3. Output Drive Capability Programmable Output Impedance (Ω (default (default N/A 7.1 V p-to-p (Min) 7.1 V p-to-p (Min) Supply Voltage Notes 2.5 V — 3.3 V — 2.5/3.3 V — 3.3 V — DD — Freescale Semiconductor ...

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... Maximum power is based on a nominal voltage of V temperature 105 °C, and an artificial smoke test The nominal recommended V The estimated power dissipation on the AV Notes MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor supply for the MPC8560 is shown in DD Table 4. MPC8560 V Power Dissipation DD 400 5.1 500 5.4 600 5 ...

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... V) Units Notes DD — — — — — — — — — — — — — — — 40 — — — — — — — — Freescale Semiconductor ...

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... This represents the total input jitter—short term and long term—and is guaranteed by design. 5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation regardless of the input frequency. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor ...

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... Symbol Min f 125 RCLK t — RCLK RCLKH RCLK Typical Max Unit 125 — MHz 8 — ns — ns 0.75 1 — =2.5V, and from 0.6 and 2.7V for DD Typical Max Unit Notes — — MHz — — — — Freescale Semiconductor Notes — — ...

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... CCB) clock. A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The CCB clock is determined by the SYSCLK × platform PLL ratio. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Table 10. RTC AC Timing Specifications Symbol Min ...

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... IO C DIO = 2.5 V ± 0.125 MHz 25° Max Unit 2.625 V 0.51 × 0.04 V REF – 0.18 V REF μA 10 — mA — mA μA 100 . REF Min Max Unit — 0 /2, V (peak to peak) = 0.2 V. OUT DD OUT Freescale Semiconductor Notes — — — Notes 1 1 ...

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... ECC (MECC[{0...7}] if n=8). 2.For timing budget analysis, the MPC8560 consumes ±550 ps of the total budget. MDQS[n] MDQ[n] Figure 4. DDR SDRAM Interface Input Timing MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor of 2.5 V ± 5%. DD Symbol Min V — ...

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... MHz 1100 266 MHz 1200 200 MHz t DDKHDX, t DDKLDX 900 333 MHz 1100 266 MHz 1200 200 MHz 0.75 × DDSHMP MCK Max Unit 10 ns 150 — 4.0 ns MCK — ps — ps 0.75 × 1.5 + 4.0 ns MCK Freescale Semiconductor Notes ...

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... Table 17. DDR SDRAM Measurement Conditions Symbol V V OUT Notes: 1.Data input threshold measurement point. 2.Data output measurement point. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor of 2.5 V ± 5 Symbol Min t 1.5 DDSHME (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... Table 18. Expected Delays for Address/Command 4 devices (12 pF) 9 devices (27 pF) 36 devices (108 pF compensation capacitor 36 devices (108 pF compensation capacitor MPC8560 Integrated Processor Hardware Specifications, Rev. 4 MCK MCK DLL Phase Alignment t DDKHOX NOOP t DDKHDS t DDKLDS DDKLDX t DDKHDX Load t MCKH t DDSHME Delay Unit 3.0 ns 3.6 ns 5.0 ns 5.2 ns Freescale Semiconductor ...

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... Input high voltage Input low voltage 1 Input high current ( Input low current (V = GND) IN Note: 1.The symbol this case, represents the LV IN MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 20. The potential applied to the input of a GMII,MII, TBI, RGMII, or RTBI Symbol –4.0 mA 4.0 mA ...

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... GTX t /t GTXH GTX t GTKHDV 3 t GTKHDX Min Max Unit 2.37 2.63 2. 0.3 DD 0.40 1. 0.3 DD –0.3 0.70 μA — 10 μA –15 — Table 1and Table 2. Min Typ Max — 8.0 — 40 — 60 2.5 — — 0.5 — 5.0 Freescale Semiconductor Unit ...

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... Table 22. GMII Receive AC Timing Specifications At recommended operating conditions with LV Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 =2.5V ± 5 Symbol 2,4 ...

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... Figure 9. GMII Receive AC Timing Diagram Min Typ Max — — 1.0 (first two letters of functional block)(signal)(state) for outputs. For example, t symbolizes GMII receive timing GRDXKL clock reference (K) going to GRX represents the GMII (G) receive GRX Ω GRXR Freescale Semiconductor Unit ns GRDVKH ...

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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 10 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 =2.5V ± 5 Symbol 2 t MTX ...

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... For example, t symbolizes MII receive timing MRDXKL clock reference (K) going to MRX represents the MII (M) receive MRX t MRXR t MRDXKH Freescale Semiconductor Unit MRDVKH ...

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... R (rise (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 12 shows the TBI transmit AC timing diagram. GTX_CLK TCG[9:0] MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 =2.5V ± 5 Symbol t ...

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... For example, t symbolizes TBI receive timing TRDXKH clock reference (K) going to TRX represents the TBI (T) receive (RX) TRX t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Freescale Semiconductor Unit TRDVKH ...

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... V and 2.0 V voltage levels. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Specifications of 2.5 V ± 5 Symbol ...

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... TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR Section 7.1, “Three-Speed Ethernet Controller (TSEC) Table 28. Symbol –1.0 mA 1.0 mA RGT t RGTH t SKRGT t SKRGT Min Max 3.13 3.47 2. 0.3 DD GND 0.50 1.70 — — 0.90 Freescale Semiconductor Unit ...

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... MHz). 3.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay and for a CCB clock of 333 MHz, the delay is 48 ns). 4.Guaranteed by design. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Symbol ...

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... mA symbol referenced in IN POR Configuration Symbol — t LBK — t LBKSKEW t MDCR Min Max 0.3 DD –0.3 0.8 — ±5 - 0.2 — DD — 0.2 Table 1 and Table 2. 1 Min Max Unit 6.0 — ns — 150 ps Freescale Semiconductor Unit V V μ Notes ...

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... Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 1 POR Configuration Symbol — t LBIVKH1 — ...

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... LBK clock reference ( high (H), with LBK of the signal in question DD 1 Min Max Unit t 6.0 — ns LBK 2.3 3.9 ns — 150 ps 5.7 — ns 5.6 — ns -1.8 — ns -1.3 — ns 1.5 — ns — -0.3 ns 1.2 Freescale Semiconductor Notes 7, 9 Notes ...

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... Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8.Guaranteed by characterization. 9.Guaranteed by design. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor POR Configuration Symbol TSEC2_TXD[6: ...

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... Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8560 Integrated Processor Hardware Specifications, Rev. 4 Ω Figure 16. Local Bus AC Test Load t LBIVKH1 t LBIVKH2 t LBKHOZ1 t t LBKHOV1 LBKHOX1 t LBKHOZ2 t t LBKHOV2 LBKHOX2 t LBKHOZ2 t t LBKHOX2 LBKHOV3 t LBOTOT t LBKHOV4 Ω t LBIXKH1 t LBIXKH2 Freescale Semiconductor ...

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... Input Signal: LGTA Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 18. Local Bus Signals (DLL Bypass Mode) MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor t LBKHKT t LBIVKH1 t LBIVKH2 t LBKLOV1 t LBKLOX1 t LBKLOV2 ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8560 Integrated Processor Hardware Specifications, Rev. 4 LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor t LBKHKT t t LBKLOX1 LBKLOV1 t LBIVKH2 ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8560 Integrated Processor Hardware Specifications, Rev. 4 LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... DC electrical characteristics for the MPC8560 CPM. Characteristic Input high voltage Input low voltage Output high voltage (I = –8.0 mA) OH Output low voltage (I = 8.0 mA) OL MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor t LBKHKT t LBKLOV1 Table 33. CPM DC Electrical Characteristics Symbol Min V 2.0 IH ...

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... TDM inputs/SI—hold time MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 44 Symbol Min V 2 — OL NOTE: Rise/Fall Time on CPM Input Pins Max Unit Notes — 0 Symbol Min Unit FIIVKH FIIXKH t 2.5 ns FEIVKH FEIXKH NIIVKH NIIXKH NEIVKH NEIXKH TDIVKH TDIXKH Freescale Semiconductor ...

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... AC timing diagrams also apply when the falling edge is the active edge. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) ...

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... FCC Output Signals (When GFMR TCI = 1) Figure 25. FCC External AC Timing Clock Diagram Figure 26 shows Ethernet collision timing on FCCs. COL/CRS (Input) Figure 26. Ethernet Collision AC Timing Diagram (FCC) MPC8560 Integrated Processor Hardware Specifications, Rev. 4 FIIXKH t FIIVKH t FIKHOX t FIKHOX t FEIXKH t FEIVKH t FEKHOX t FEKHOX t FCCH Freescale Semiconductor ...

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... Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor t NEIXKH t NEKHOX t ...

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... C Bus Timing. t SCHCL t SCLDX t t SRISE SFALL 2 Figure 30. CPM I C Bus Timing Diagram Max Unit 1 F MAX BRGCLK/48 ) — SCL ) — SCL ) — SCL ) — SCL ) — SCL ) — SCL ) — SCL 1/( SCL 1/( SCL ) — SCL t SDVCH t SCHDH Freescale Semiconductor ...

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... Start condition hold time 2 Data hold time 2 Data setup time SDA/SCL rise time SDA/SCL fall time Stop condition setup time MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor parameters clock value of 100 kHz and 400 kHz Timing (f = 100 kHz) SCL ...

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... Min Max Unit Notes 0 33.3 MHz 30 — — — — 0 — — 25 — — the midpoint of the signal in TCLK (first two letters of functional block)(signal)(state) for outputs. For example, symbolizes JTAG JTDXKH clock reference (K) JTG Freescale Semiconductor — — — ...

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... TRST Figure 34 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor = 50 Ω JTKHKL t JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD /2) Figure 33 ...

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... C DC Electrical Characteristics of 3.3 V ± 5%. DD Symbol Min 0.7 × –0 I2KHKL I –10 I (max — switched off JTIXKH Input Data Valid Output Data Valid 2 C interface of the MPC8560. Max Unit Notes 0.3 × 0.2 × μ Freescale Semiconductor — — — ...

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... LOW period (t I2DVKH 4.C = capacitance of one bus line in pF. B 6.Guaranteed by design. Figure 16 provides the AC test load for the I Output MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 2 C interface of the MPC8560. 2 Table 41 Electrical Specifications Table 40). Symbol f ...

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... MPC8560 Integrated Processor Hardware Specifications, Rev. 4 bus I2DVKH I2KHKL t I2SXKL t t I2CH I2SVKH t I2DXKL Sr 2 Figure 37 Bus AC Timing Diagram Symbol Min –0 — – 0 — OL symbol referenced I2CF t I2CR t I2PVKH Max Unit 0.8 V μA ±5 — V 0.2 V Table 1 and Table 2. Freescale Semiconductor ...

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... HRESET. 7.The timing parameter t PCRHFV Bus Specifications . 8.The reset assertion timing requirement for HRESET is 100 μs. 9.Guaranteed by characterization. 10.Guaranteed by design. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Table 43 provides the PCI AC timing specifications at 1 Symbol t PCKHOV t ...

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... Z 0 Figure 38. PCI/PCI-X AC Test Load t PCIVKH CLK t PCKHOV t PCKHOZ Output Symbol t PCKHOV t PCKHOX t PCKHOZ t PCIVKH t PCIXKH t PCRVRH t PCRHRX t PCRHFV Ω PCIXKH Min Max Unit — 3.8 ns 0.7 — ns — 1.7 — ns 0.5 — — clocks — clocks Freescale Semiconductor Notes ...

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... Input setup time to SYSCLK Input hold time from SYSCLK REQ64 to HRESET setup time HRESET to REQ64 hold time HRESET high to first FRAME assertion PCI-X initialization pattern to HRESET setup time MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Symbol Min Max t 10 — ...

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... PCI-X 1.0a of 3.3 V ± 5%. DD Symbol V OHD V OLD ΔV OSD V OHCM V OLCM Min Max Unit Notes and t only in PCI-X mode. In CYC Table 46 and Table 47, Min Max Unit 247 454 mV –454 –247 mV — 1.125 1.375 V 1.125 1.375 V Freescale Semiconductor 6, 12 Notes 1 ...

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... Differential input high voltage Differential input low voltage Common mode input range (referenced to receiver ground) Input differential resistance Notes: 1.Over the common mode range. 2.Limited See Figure 48. I MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5%. DD Symbol ΔV OSCM R TERM | ...

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... B. OB Figure 41. DC Driver Signal Levels n the settings of the LGPL[0:1] signals at reset. Note that the dependent o Figure defined defined – )/ ΔV OS 1.375 V 1.125 V Common-Mode Specifications (c) shows how the signals are defined. The – – Freescale Semiconductor ...

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... With the transmit output (or receiver input) eye diagram, the user can determine if the transmitter output (or receiver input) is compliant with an oscilloscope with the appropriate software. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor RapidIO 61 ...

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... Differential output low voltage MPC8560 Integrated Processor Hardware Specifications, Rev. 4 1–X2 Time (UI) Figure 43. Example Compliance Mask Table 48, Table 49, and Symbol Min V 200 OHD V –540 OLD 1–X1 1 Table 50. A driver shall comply Range Unit Notes Max 540 mV 1 –200 mV 1 Freescale Semiconductor ...

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... Skew of single data outputs to associated clock Notes: 1.See Figure 44. 2.Requires ±100 ppm long term frequency stability. 3.Measured 4.Measured using the RapidIO transmit mask shown in 5.See Figure 49. 6.Guaranteed by design. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Range Symbol Min Max 200 — FALL t 200 — ...

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... DV t DPAIR t SKEW,PAIR Figure 44. )/2. A signal is compliant with the data valid min Time (UI) Figure 44. RapidIO Transmit Mask Range Unit Min Max 200 540 mV –540 –200 100 — ps 100 — ps 575 — ps — 100 ps –100 100 ps Figure 1–X2 1 Freescale Semiconductor Notes 44. The ...

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... If skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope trigger point – Oscilloscope (Recording) Trigger Point Figure 45. Example Driver Output Eye Pattern MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 1.0 UI 1.0 UI Eye Used for Compliance Eye Pattern Testing RapidIO 65 ...

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... A receiver shall comply with the Range Symbol Min 1080 t — DPAIR t –300 SKEW,PAIR Figure 46. Range Symbol Min 600 t — DPAIR t –267 SKEW,PAIR Figure 46. Unit Notes Max 380 ps 3 300 ps 4 Unit Notes Max — 400 ps 3 267 ps 4 Freescale Semiconductor ...

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... RapidIO receive mask to one that does not. Each data signal in the interface shall be carrying random or pseudo-random data when the recordings are made. If pseudo-random data is used, the length of the pseudo-random sequence (repeat length) shall be long MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Symbol Min DC ...

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... If skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope trigger point. 0 – Oscilloscope (Recording) Trigger Point Figure 47. Example Receiver Input Eye Pattern MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 68 1.0 UI 1.0 UI Eye Used for Compliance Eye Pattern Testing Freescale Semiconductor ...

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... Center Point for Clock Center point of the data valid window of the earliest allowed data bit for data grouped late with respect to clock D[0:7]/D[8:15], FRAME MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 1.0 UI Nominal 0 SKEW,PAIR 0.5 DV Eye Opening DV Figure 48. Data to Clock Skew 1 ...

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... Die size Package outline Interconnects Pitch Minimum module height Maximum module height Solder Balls Ball diameter (typical) MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 70 12.2 mm × 9 × 783 1 mm 3. Sn/36 Pb/2 Ag 0.5 mm Freescale Semiconductor ...

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... MPC8560, 783 FC-PBGA package. Figure 50. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8560 FC-PBGA 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor NOTES Package and Pin Listings 71 ...

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... AD10 V11 AH10 AA9 AE13 AD13 W11 Y11 AF5 AF3, AE4, AG4, AE5 AE6 AG5, AH5, AF6, AG6 Power Pin Type Notes Supply I I I/O OV — DD I/O OV — — I/O OV — — DD I/O OV — Freescale Semiconductor ...

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... LALE LBCTL LCKE LCLK[0:2] LCS[0:4] LCS5/DMA_DREQ2 MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Package Pin Number DDR SDRAM Memory Interface F13, H13, A13, B12 N20, M20, L19, E19, C21, A21, G19, A19 B18, B19 K19, B25, D27, J14, J13 ...

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... AB28, AB27 T23, P24 DMA H5, G4 H6, G5 H7, G6 Programmable Interrupt Controller AG17 AG16 AB20 Y20 AF26 AH24 AB21 Ethernet Management Interface F1 E1 Power Pin Type Notes Supply I I — — — — — — — — I I I/O OV — DD Freescale Semiconductor ...

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... Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_TXD[7:2] TSEC2_TXD[1:0] TSEC2_TX_EN TSEC2_TX_ER TSEC2_TX_CLK TSEC2_GTX_CLK TSEC2_CRS TSEC2_COL TSEC2_RXD[7:0] TSEC2_RX_DV TSEC2_RX_ER TSEC2_RX_CLK RIO_RCLK RIO_RCLK MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Package Pin Number Gigabit Reference Clock E2 A6, F7, D7, C7 B7, A7, G8 D4, B4, D3, D5, B5, A5, F6 ...

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... AH23 System Control AH16 AG20 AF20 M11 G1 Debug N12 G2 J9, G3 F3, F5 Clock AH21 AB23 AF22 Power Pin Type Notes Supply I OV — — — — — — — — — — — — — — — — — Freescale Semiconductor ...

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... C28, D16, D19, D21, D24, D28, E17, E22, F12, F15, F19, F25, G13, G18, G20, G23, G28, H19, H24, J12, J17, J22, J27, K15, K20, K25, L13, L23, L28, M25, N21 MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Package Pin Number JTAG AF21 ...

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... Ethernet I/O (2.5 V, 3.3 V) Reference Voltage MV — REF Signal; DDR — — 16 PCI/PCI-X, OV — DD RapidIO, 10/100 Ethernet, and other Standard (3.3 V) — — 15 Power for Core (1.2 V) — — 13 Power for Core V — DD (1.2 V) I/0 OV — DD I/0 OV — DD I/0 OV — DD Freescale Semiconductor ...

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... OVDD for normal machine operation. 22.If this signal is used as both an input and an output, a weak pull-up (~10 kΩ) is required on this pin. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Package Pin Number AC1, AD1, AD2, AD5, AD6, AE3, AE2 ...

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... Ratio,” and Section 15.3, “e500 Core PLL Table 56 provides the clocking 1 GHz Unit Notes Min Max 400 1000 MHz Ratio,” for ratio 1 GHz Unit Notes Min Max 100 166 MHz Ratio,” for ratio Freescale Semiconductor ...

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... This ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in Binary Value of LALE, LGPL2 Signals MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Table 57. Table 57. CCB Clock Ratio ...

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... Platform/CCB Frequency (MHz) 200 267 208 333 200 250 267 333 300 333 Table 60. Package Thermal Characteristics 83 100 111 133.33 200 222 267 250 300 333 333 Symbol Value Unit Notes °C θJMA °C θJMA R 12 °C θJMA R 7.5 °C/W 3 θJB Freescale Semiconductor ...

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... The system board designer can choose between several types of heat sinks to place on the MPC8560. There are several commercially-available heat sinks from the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Figure 51. The heat sink should be attached to the printed-circuit FC-PBGA Package Heat Sink Heat Sink Clip ...

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... W/m•K. The nickel plated copper lid is modeled as 12x14x1 mm. Note that the die and lid are not centered on the substrate; there is a 1.5 mm offset documented in the case outline drawing in Figure 50. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 84 408-749-7601 818-842-7277 408-436-8770 800-522-6752 603-635-5102 Figure 52. Five cuboids are used Freescale Semiconductor ...

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... Internal Package Conduction Resistance For the packaging technology, shown in are as follows: • The die junction-to-case thermal resistance • The die junction-to-board thermal resistance MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Unit W/(m × K) 360 360 z 360 Side View of Model (Not to Scale) ...

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... The use of an adhesive for heat sink attach is not recommended. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 86 Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Leads Radiation Convection C with an air gun can soften the ° Freescale Semiconductor ...

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... S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company th 18930 West 78 St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Contact Pressure (psi) ...

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... J = 0.8, and a power consumption ( 30°C + 5°C + (0.8°C/W + 1.0°C/W + θ versus airflow velocity for a Thermalloy heat sink SA of about 3.3°C/W, thus SA+ ) may be in the range of 5° may be about 1°C/W. Assuming a INT ) of 7.0 W, the D ) × 7 Freescale Semiconductor ) A ...

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... For applications with significant vibration requirements, silicone damping material can be applied between the heat sink and plastic frame. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Thermalloy #2328B Pin-fin Heat Sink (25 × 28 × 15 mm) 0 ...

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... Figure 56 and Figure 57 Figure 56. Exploded Views ( Heat Sink Attachment using a Plastic Force MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 90 provide exploded views of the plastic fence, heat sink, and spring clip. Freescale Semiconductor ...

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... For these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Thermal 91 ...

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... MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 92 Section 15.2, “Platform/System PLL Ratio.” Section 15.3, “e500 Core PLL Ratio.” level should always be equivalent through a low frequency filter scheme such as the DD Figure 58, one to each of the three AV pin being supplied to minimize and preferably DD pins Freescale Semiconductor ...

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... GND. Then, the value of each resistor is varied until the pad voltage is OV output impedance is the average of two components, the resistances of the pull-up and pull-down devices. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 10 Ω 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 58 ...

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... Table 61. Impedance Characteristics PCI/PCI-X 25 Target 25 Target NA NA Table 105°C. j and R are designed to be close to each SW2 SW1 . The measured voltage is term × source term 1 2 DDR DRAM RapidIO Symbol 20 Target Target 200 Target Z DIFF Freescale Semiconductor – 1). The , DD Unit ...

Page 95

... LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal machine operation. Refer to the PCI 2.2 specification for all pull-ups required for PCI. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 2 C open drain type pins should be pulled up with ~1 kΩ resistors. System Design Information ...

Page 96

... IC). Regardless of the numbering, the signal placement recommended in all known emulators. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 96 allows the COP port to independently assert HRESET or TRST, Figure 60, for connection to the target system, and is Figure 60 is common to Freescale Semiconductor ...

Page 97

... JTAG interface may need to be wired onto the system in future debug situations. • Tie TCK to OV through a 10 kΩ resistor. This will prevent TCK from changing state and DD reading incorrect data into the device. • No connection is required for TDI, TMS, or TDO. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor COP_TDO COP_TDI 3 4 ...

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... COP_TRST 10 Ω 2 COP_VDD_SENSE NC COP_CHKSTP_OUT 10 kΩ COP_CHKSTP_IN COP_TMS COP_TDO COP_TDI COP_TCK 10 kΩ Figure 61. JTAG Interface Connection kΩ 6 SRESET 1 10 kΩ HRESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST CKSTP_OUT 10 kΩ CKSTP_IN TMS TDO TDI TCK Freescale Semiconductor ...

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... Changed parameter “Clock cycle duration” to “Clock period” in Added note LBKHOV1 Updated LALE signal in Modified Figure 21. Modified Figure 61. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Table 62. Document Revision History Substantive Change(s) and paragraph above it. Table 1. Table 2. Table 63 Table 1. ...

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... Section 16.2.3, “Thermal Interface Table 63. Table 5. Table 16 and t parameters in MDKHDV MDKHDX parameter in Table 31 and Table Specifications”. Table 23, and Table 24. 23, Table 24, Table 25, Table 26, and Specifications”. Specifications”. and Figure 25. Materials”. Table 29. 32, and updated Figure 17. Table 54. Freescale Semiconductor Table 27. ...

Page 101

... Section 14.1— Changed minimum height from 2.22 to 3.07 and maximum from 2.76 to 3.75 Section 16.2.4.1—Changed Section 17.7—Added paragraph that begins “TSEC1_TXD[3:0]...” MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Substantive Change(s) power table ...

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... Addition of CPM to OV and OV DD VREF DISKEW MCKSKEW2 20—Modified “conditions” for I and I IH 19—Changed LSYNC_IN to Internal clock at top of each figure t , and t FIIVKH, NIIVKH TDIVKH t t FEKHOX, NIKHOX, NEKHOX, LBKHOX3 ; Addition of SYSCLK addition of t and t . PIIVKH PIIXKH t ; addition of t TDKHOX PIKHOX. Freescale Semiconductor ...

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... Section 1.11.3—Updated pin list table: LGPL5/LSDAMUX to LGPL5, LA[27:29] and LA[30:31] to LA[27:31], TRST to TRST, added GBE Clocking section and EC_GTX_CLK125 signal. Figure 50—Updated pin 2 connection information. 1 Original Customer Version. MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Substantive Change(s) Document Revision History 103 ...

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... AQ = 1.0 GHz VT = FC-PBGA (Pb-free) Listings” for more information on available package types Platform Revision Level 3, 4 Frequency L = 333 MHz B = Rev. 2.0 J= 266 MHz (SVR = 0x80700020 Rev. 2.1 (SVR = 0x80700021 333 MHz B = Rev. 2.0 (SVR = 0x80700020 Rev. 2.1 (SVR = 0x80700021) Freescale Semiconductor ...

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... CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. YWWLAZ is the assembly traceability code. Figure 62. Part Marking for FC-PBGA Device MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Figure 62. MPC85nn MPCnnnntppfffcr ...

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... Device Nomenclature THIS PAGE INTENTIONALLY LEFT BLANK MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 106 Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor Device Nomenclature 107 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...