MPC8560CPX667JC Freescale Semiconductor, MPC8560CPX667JC Datasheet - Page 93

IC MPU PWRQUICC III 783-FCPBGA

MPC8560CPX667JC

Manufacturer Part Number
MPC8560CPX667JC
Description
IC MPU PWRQUICC III 783-FCPBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC IIIr
Datasheets

Specifications of MPC8560CPX667JC

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
667MHz
Embedded Interface Type
I2C, MII, SPI, TDM, UTOPIA
Digital Ic Case Style
BGA
No. Of Pins
783
Rohs Compliant
No
Family Name
MPC85XX
Device Core
PowerQUICC III
Device Core Size
32b
Frequency (max)
667MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2V
Operating Supply Voltage (max)
1.26V
Operating Supply Voltage (min)
1.14V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
783
Package Type
FCBGA
For Use With
MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8560CPX667JC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure 58
17.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8560 can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8560 system, and the MPC8560
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V
MPC8560. These decoupling capacitors should receive their power from separate V
LV
be placed directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
17.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
the MPC8560.
17.5 Output Buffer DC Impedance
The MPC8560 drivers are characterized over process, voltage, and temperature. There are two driver
types: a push-pull single-ended driver (open drain for I
current-steering differential driver for the RapidIO port.
To measure Z
or GND. Then, the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
Freescale Semiconductor
DD
, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may
shows the PLL power supply filter circuit.
DD
0
for the single-ended drivers, an external resistor is connected from the chip pad to OV
, OV
V
DD
DD
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
, GV
DD
Figure 58. PLL Power Supply Filter Circuit
, and LV
10 Ω
DD
2.2 µF
planes, to enable quick recharging of the smaller chip
GND
DD
Low ESL Surface Mount Capacitors
2
, GV
C) for all buses except RapidIO, and a
2.2 µF
DD
DD
, OV
DD
, or LV
, GV
DD
AV
, GV
DD
DD
DD
, LV
(or L2AV
as required. Unused active high
DD
DD
, and LV
DD
, OV
DD
/2 (see
)
System Design Information
DD
DD
DD
, and GND pins of
, OV
Figure
pins of the
DD
, GV
59). The
DD
DD
,
93

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