MPC8560CPX667JC Freescale Semiconductor, MPC8560CPX667JC Datasheet - Page 66

• Manufacturer Part Number: MPC8560CPX667JC
• Description: IC MPU PWRQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIIr

Specifications of MPC8560CPX667JC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, MII, SPI, TDM, UTOPIA
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Rohs Compliant: No
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

RapidIO
13.3.2 RapidIO Receiver AC Timing Specifications
The RapidIO receiver AC timing specifications are provided in
specifications for each data rate/frequency for which operation of the receiver is specified. Unless
otherwise specified, these specifications are subject to the following conditions.
66
Duty cycle of the clock input
Data valid
Allowable static skew between any two data inputs
within a 8-/9-bit group
Allowable static skew of data inputs to associated clock
Notes:
1.Measured at V
2.Measured using the RapidIO receive mask shown in
3.See
4.See
5.Guaranteed by design.
Duty cycle of the clock input
Data valid
Allowable static skew between any two data inputs
within a 8-/9-bit group
Allowable static skew of data inputs to associated clock
Notes:
1.Measured at V
2.Measured using the RapidIO receive mask shown in
3.See
4.See
5.Guaranteed by design.
•
•
•
•
•
Figure
Figure 48
Figure
Figure 48
The specifications apply over the supply voltage and ambient temperature ranges specified by the
device vendor.
The specifications apply for any combination of data patterns on the data signals.
The specifications apply over the receiver common mode and differential input voltage ranges.
Clock specifications apply only to clock signals.
Data specifications apply only to data signals (FRAME, D[0:7])
49.
49.
ID
ID
and
and
Table 51. RapidIO Receiver AC Timing Specifications—500 Mbps Data Rate
Table 52. RapidIO Receiver AC Timing Specifications—750 Mbps Data Rate
= 0 V.
= 0 V.
Characteristic
Characteristic
Figure
Figure
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
49.
49.
Figure
Figure
t
t
SKEW,PAIR
Symbol
SKEW,PAIR
Symbol
t
t
DPAIR
46.
DPAIR
DC
46.
DV
DC
DV
Table
1080
–300
–267
Min
Min
600
47
—
47
—
51. A receiver shall comply with the
Range
Range
Max
Max
380
300
400
267
53
53
—
Freescale Semiconductor
Unit
Unit
ps
ps
ps
ps
ps
ps
%
%
Notes
Notes
1, 5
1, 5
2
3
4
2
3
4