PCX8240VTPU200EZD3 Atmel, PCX8240VTPU200EZD3 Datasheet - Page 22

• Manufacturer Part Number: PCX8240VTPU200EZD3
• Description: IC MPU 32BIT 200MHZ 352TBGA
• Manufacturer: Atmel

Specifications of PCX8240VTPU200EZD3

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Output AC Timing
Specification
Table 11. Output AC Timing Specifications
Notes:
22
Num
12b1
12b2
12b3
12a
12c
12d
13a
13b
14a
14b
1. All memory and related interface output signal specifications are specified from the V
2. All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.285*OVdd or 0.615*OVdd of the signal
3. All output timings assume a purely resistive 50
4. PCI Bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0 – 3], PAR, TRDY, FRAME, STOP,
5. PCI hold times can be varied, see “PCI Signal Output Hold Timing” on page 23 for information on programmable PCI output
6. These specifications are for the default driver strengths indicated in Table 7 on page 17.
Characteristics
PCI_SYNC_IN to Output Valid, 66 MHz PCI, with MCP pulled-down
to logic 0 state. See Figure 14.
PCI_SYNC_IN to Output Valid, 33 MHz PCI, with MCP in the default
logic 1 state. See Figure 14.
SDRAM_SYNC_IN to Output Valid
(For Memory Control and Data Signals accessing DRAM in Flow
Through Mode)
SDRAM_SYNC_IN to Output Valid
(For Memory Control and Data Signals accessing DRAM in
Registered
Mode)
SDRAM_SYNC_IN to Output Valid
(For Memory Control and Data Signals accessing non-DRAM)
SDRAM_SYNC_IN to Output Valid (For All Others)
SDRAM_SYNC_IN to Output Valid (For Two-wire Interface)
Output Hold, 66 MHz PCI, with MCP and CKE pulled-down to logic 0
states. See Table 12.
Output Hold, 33 MHz PCI, with MCP in the default logic 1 state and
CKE pulled-down to logic 0 state. See Table 12.
Output Hold (For All Others)
PCI_SYNC_IN to Output High Impedance (For PCI)
SDRAM_SYNC_IN to Output High Impedance (For All Others)
PC8240
ory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on
every rising and falling edge of PCI_SYNC_IN). See Figure 10 on page 21.
in question for 3.3V PCI signaling levels. See Figure 11 on page 21.
time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
DEVSEL, PERR, SERR, AD[0 – 31], REQ[4 – 0], GNT[4 – 0], IDSEL, INTA.
hold times. The values shown for item 13a are for PCI compliance.
(3)(6)
Table 11 provides the processor bus AC timing specifications for the PC8240. See Fig-
ure 10 on page 21 and Figure 11 on page 21.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V
and LVdd = 3.3V ± 5%
load (See Figure 13 on page 23). Output timings are measured at the pin;
Min
0.5
2.0
–
–
–
–
–
–
–
0
–
–
M
= 1.4V of the rising edge of the mem-
TBD
TBD
TBD
TBD
TBD
Max
6.0
8.0
7.0
7.0
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2149A–HIREL–05/02
Notes
(2)(4)(5)
(2)(4)(5)
(2)(4)
(2)(4)
(2)(4)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
± 5%