PCX8240VTPU200EZD3 Atmel, PCX8240VTPU200EZD3 Datasheet - Page 38

• Manufacturer Part Number: PCX8240VTPU200EZD3
• Description: IC MPU 32BIT 200MHZ 352TBGA
• Manufacturer: Atmel

Specifications of PCX8240VTPU200EZD3

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descrip-
t i o n s
o f
t h e
P C 8 2 4 0
a r e
a v a i l a b l e
o n
t h e
i n t e r n e t
a t
www.mot.com/SPS/PowerPC/teksupport/tools/BSDL/) The TRST signal is optional in
the IEEE 1149.1 specification but is provided on all PowerPC implementations. While it
is possible to force the TAP controller to the reset state using only the TCK and TMS
signals, more reliable power-on reset performance will be obtained if the TRST signal is
asserted during power-on reset. Since the JTAG interface is also used for accessing the
common on-chip processor (COP) function of PowerPC processors, simply tying TRST
to HRST_CPU/HRST_CTRL is not practical. Note that the two hard reset signals on the
PC8240 (HRST_CPU and HRST_CTRL) must be asserted and negated together to
guarantee normal operation.
The common on-chip processor (COP) function of PowerPC processors allows a remote
computer system (typically a PC with dedicated hardware and debugging software) to
access and control the internal operations of the processor. The COP interface con-
nects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert
HRST_CPU/HRST_CTRL or TRST in order to fully control the processor. If the target
system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 28 allows the COP to independently assert
HRST_CPU/HRST_CTRL or TRST while ensuring that the target can drive
HRST_CPU/HRST_CTRL as well. The shown COP header, adds many benefits includ-
ing breakpoints, watchpoints, register and memory examination/modification and other
standard debugger features are possible through this interface. Availability of these fea-
tures can be as inexpensive as an unpopulated footprint for a header to be added when
needed.
PC8240
38
2149A–HIREL–05/02