PCX8240VTPU200EZD3 Atmel, PCX8240VTPU200EZD3 Datasheet - Page 26

• Manufacturer Part Number: PCX8240VTPU200EZD3
• Description: IC MPU 32BIT 200MHZ 352TBGA
• Manufacturer: Atmel

Specifications of PCX8240VTPU200EZD3

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 14. PC8240 Maximum Two-wire Interface Input Frequency (Continued)
Notes:
Table 15. Two-wire Interface Output AC Timing Specifications
Notes:
26
Num
1
2
3
4
5
6
7
8
9
16, 17, 3A, 3B, 3C, 3D
1A, 1B, 3E, 3F
1. Values are in kHz unless otherwise specified.
2. FDR Hex and Divider (Dec) values are listed in corresponding order.
3. Multiple Divider (Dec) values will generate the same input frequency but each Divider (Dec) value will generate a unique
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency
3. Since SCL and SDA are open-drain type outputs, which the PC8240 can only drive low, the time required for SCL or SDA to
FDR Hex
PC8240
Characteristics
Start condition hold time
Clock low period
SCL/SDA rise time (from 0.5V to 2.4V)
Data hold time
SCL/SDA fall time (from 2.4V to 0.5V)
Clock high time
Data setup time (PC8240 as a master only)
Start condition setup time (for repeated start
condition only)
Stop condition setup time
1C, 1D
1E, 1F
14, 15
18, 19
output frequency as shown in Table 15 on page 26.
Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified
SCL and SDA are delayed signals from what is seen in real time on the
signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is
added to the value in the table (where this note is referenced). See Figure 16 on page 27.
reach a high level depends on external signal capacitance and pull-up resistor values.
(2)
12288, 14336, 15360,
24576, 28672, 30720,
16384, 20480, 24576
Table 15 provides the two-wire interface output AC timing specifications for the PC8240.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ± 5%
and LVdd = 3.3V ± 5%
Divider (Dec)
18432, 20480
36864, 40960
49152, 61440
9216, 10240
32768
(2)
SDRAM_CLK
D
(D
at 25 MHz
FDR
(FDR[5] == 0) x (D
(FDR[5] == 1) x (D
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
FDR
1({FDR[5],FDR[1]} == b’01))
8.0 + (16 x 2
16
12
8
6
4
3
+ (Output start condition hold
/2) - (Output data hold time)
Max Two-wire Interface Input Frequency
D
D
time)
Min
FDR
FDR
4.0
–
SDRAM_CLK
FDR[4:2]
/2
/2
at 33 MHz
two-wire interface
FDR
FDR
21
16
10
/16)/2N +
) x (5 -
8
5
4
/16)/2M
SDRAM_CLK
at 50 MHz
bus. The qualified SCL, SDA
Max
32
24
16
12
< 5
8
6
–
–
–
–
–
–
–
–
CLKs
CLKs
CLKs
CLKs
CLKs
CLKs
CLKs
Unit
mS
ns
2149A–HIREL–05/02
SDRAM_CLK
(1)
at 100 MHz
64
48
32
24
16
12
Notes
(1)(2)(5)
(1)(2)(5)
(1)(2)(5)
(1)(2)(5)
(1)(2)(5)
(1)(5)
(1)(2)
(3)
(4)