MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 135

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

4.6.6 Slave (Disable CPU32+) Mode Bus Exceptions
The reset and bus error master mode support also applies to the slave mode. There is a
difference, however, in supporting halt and retry as explained in the following paragraphs.
4.6.6.1 HALT. The QUICC transfer operation may be suspended at any time by asserting
HALT to the QUICC. In response, any bus cycle in progress is completed (after DSACKx is
asserted), and bus ownership is released. No further bus cycles will be started while HALT
remains asserted. When the QUICC is in the middle of an operand transfer when halted and
when a new transfer request is pending, the QUICC will arbitrate for the bus and continue
normal operation.
4.6.6.2 RETRY. When HALT and BERR are asserted during a bus cycle, the QUICC termi-
nates the bus cycle, releases the bus, and suspends any further operation until these signals
are negated. The QUICC will then arbitrate for the bus, re-execute the previous bus cycle,
and continue normal operation. Thus, in slave mode, a retry is actually a relinquish and retry.
4.6.7 Internal Accesses
The QUICC supports an external-master access to its internal registers with a glueless inter-
face. The QUICC internal register port size is always 32 bits. External QUICC/MC68EC030
accesses have the same bus operation as the QUICC (see 4.3 Data Transfer Cycles). The
QUICC supports the interrupt acknowledge cycles presented in 4.4.4 Interrupt Acknowledge
Bus Cycles. The QUICC also supports the MC68EC040 read and write accesses and inter-
rupt acknowledge cycles (see Figure 4-41–Figure 4-44).
MOTOROLA
When the QUICC is doing a word access to an 8-bit port and
HALT is asserted during the first access to an 8-bit port, the
QUICC will access this byte again after bus ownership is granted
to the QUICC.
In slave mode HALT has more priority than bus coherency,
whereas in normal mode (CPU32+ is enabled) HALT has less
priority than bus coherency.
When the relinquish and retry is asserted during a word access
to an 8-bit port, and the external master that takes the bus per-
forms an external-to-internal bus cycle, the entire word access
will be retried. This is true even if the relinquish and retry was
asserted on the second access and the first 8-bit access was
completed normally.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
NOTE
Bus Operation
4-59