MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 912

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Performance
A-2
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
These numbers are estimates generated prior to silicon. Additional work will be performed to improve the
accuracy of the SCC performance numbers and will be reported in later revisions of this manual.
All performance calculations assume a 25-MHz system clock and sync clock for the SCCs. The results scale
linearly with different system clock speeds. A change in the sync clock will not affect performance as long as
the required 1:2.25 or 1:2.5 ratio is maintained.
User should consult with receive and transmit clock timing of the SIA to ensure clock pulse width high and
width low are satisfied for high speed serial communications.
In all cases, the numbers assume data is stored in external system RAM.
The performance is not expected to degrade based on the number of wait states in the system, as long as the
system RAM has between 0 and 9 wait states.
The performance table is also applicable when the time-slot assigner on the QUICC is used.
When the performance of a high-speed channel together with a low-speed channel was measured, the high-
speed channel was always SCC1.
Performance in HDLC bus mode is the same as HDLC performance, for both full duplex and half duplex
operation. (Half duplex is the normal configuration of HDLC bus mode, thus HDLC half duplex performance
numbers would normally be used.)
All results assume that the other RISC features are not operating—i.e., the RISC timer tables, the IDMA auto
buffer and buffer chaining modes, the parallel interface port, and the other serial channels. If these features
are operating, performance may be slightly reduced. The DRAM refresh controller has no effect on the
performance.
Except for Ethernet, all table results assume continuous full-duplex operation. Results for half-duplex
operation are roughly 2x better.
The SMC performance results are without the SCCs operating; otherwise, SMC performance may be
reduced. Although the exact SMC performance that can be obtained is determined by many RISC utilization
factors and is therefore difficult to estimate, it is expected that 9.6 kbps on both SMC UARTs could be
simultaneously supported in most situations.
4 UART-S
4 BISYNC
Number
1 HDLC
2 HDLC
3 HDLC
4 HDLC
1 ENET
1 ENET
2 ENET
4 UART
1 TRAN
2 TRAN
3 TRAN
4 TRAN
2 TRAN
2 UART
High-Speed Channels
2.05 Mbps
2.05 Mbps
1.56 Mbps
2.6 Mbps
2.6 Mbps
625 kbps
625 kbps
460 kbps
100 kbps
10 Mbps
10 Mbps
10 Mbps
8 Mbps
4 Mbps
8 Mbps
4 Mbps
Speed
Freescale Semiconductor, Inc.
For More Information On This Product,
Number
MC68360 USER’S MANUAL
3 HDLC
2 HDLC
1 HDLC
Low-Speed Channels
Go to: www.freescale.com
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2.05 Mbps
2.05 Mbps
1 Mbps
Speed
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Minor restrictions on HDLC buffer length
Async SCC
Sync UART SCC
SMC Channels
SMC Channels
Comments/Restrictions
MOTOROLA