MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 480

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
channel counts the number of consecutive idle characters received. If the count reaches the
value programmed into MAX_IDL, the buffer is closed, and an RX interrupt is generated. If
no receive buffer is open, this event does not generate an interrupt or any status information.
The internal idle counter (IDLC) is reset every time a character is received.
Framing Error . A framing error is detected by the UART controller when a character is
received with no stop bit. All framing errors are report by the UART controller, regardless of
the UART mode. When this error occurs, the channel writes the received character to the
buffer, closes the buffer, sets the FR bit in the BD, and generates the RX interrupt (if
enabled). The channel also increments the FRMEC. When this error occurs, parity is not
checked for this character. In automatic multidrop mode, the receiver enters hunt mode
immediately.
If the RZS bit is set in the UART mode register when the UART is in the synchronous mode
(SYN is set), then the receiver reports all framing errors, but continues reception with the
assumption that the unexpected zero is really the start bit of the next character. If RZS is
set, user software may not wish to consider a reported UART framing error as a true UART
framing error, unless two or more framing errors occur within a short period of time.
Break Sequence . The UART offers very flexible break support for the receiver. When the
first break sequence is received (one or more all-zero characters), the UART increments the
BRKEC and issues the break start (BRKs) event in the UART event register, which can gen-
erate an interrupt (if enabled). The UART then measures the break length, and, when the
break sequence is complete, writes the length to the BRKLN register. After the first one is
received, the UART also issues the break end (BRKe) event in the UART event register,
which can generate an interrupt (if enabled). If the UART was in the process of receiving
characters when the break was received, it will also close the receive buffer, set the BR bit
in the Rx BD, and write the RX bit in the event register, which can generate an interrupt (if
enabled).
If the RZS bit is set in the UART mode register when the UART is in the synchronous mode
(SYN is set), then a break sequence will be detected only after two successive break char-
acters are received.
7.10.16.15 UART MODE REGISTER (PSMR). Each PSMR is a 16-bit, memory-mapped,
read-write register that controls SCC operation. When the SCC is configured as a UART,
this register is called the UART mode register. This register is cleared at reset. Many of the
PSMR bits may be modified on the fly (i.e., while the receiver and transmitter are enabled).
7-156
FLC
15
SL
14
13
To disable the idle sequence function entirely, set the MAX_IDL
value to zero.
CL
12
11
Freescale Semiconductor, Inc.
For More Information On This Product,
UM
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
FRZ
9
RZS
NOTE
8
SYN
7
DRT
6
—
5
PEN
4
3
RPM
2
MOTOROLA
1
TPM
0