MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 699

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.15.4 Interrupt Vector Generation and Calculation
Pending unmasked CPM interrupts are presented to the CPU32+ core in order of priority.
The CPU32+ core responds to an interrupt request by initiating an interrupt acknowledge
cycle to receive a vector number, which allows the core to locate the interrupt’s service rou-
tine. For CPM interrupts, the CPIC passes an interrupt vector corresponding to the highest
priority, unmasked, pending interrupt. The CPM always generates a vector during an inter-
rupt acknowledge cycle at its interrupt level, regardless of whether the QUICC is in normal
mode or slave mode.
The three MSBs of the interrupt vector number are programmed by the user in the CIMR.
These three bits are concatenated with five bits generated by the CPIC to provide an 8-bit
vector number to the CPU32+ core. The CPIC’s encoding of the five low-order bits of the
interrupt vector is listed in Table 7-22.
Note that the interrupt vector table is the same as the CPM interrupt priority table except for
two differences. First, the lower five bits of the SCC vectors are fixed; they are not affected
by the SCC group or spread mode or the relative priority order of the SCCs. Second, an error
MOTOROLA
EVENT
MASK
BIT
BIT
SCCM
SCCE
Figure 7-100. Interrupt Request Masking
Freescale Semiconductor, Inc.
For More Information On This Product,
(13 EVENT BITS)
13 INPUT
MC68360 USER’S MANUAL
OR
Go to: www.freescale.com
MASK
BIT
CIMR
CIPR
(28 CIPR BITS)
28 INPUT
OR
CPM Interrupt Controller (CPIC)
REQUEST
TO THE IMB
AT THE
LEVEL
SPECIFIED
IN IRL2–IRL0
IN THE CICR.
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