MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 103

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

BERR is recognized during a bus cycle in any of the following cases:
When the processor recognizes a bus error condition, it terminates the current bus cycle
in the normal way. Figure 5-38 shows the timing of a bus error for the case in which
DSACK1/DSACK0 is not asserted. Figure 5-39 shows the timing for a bus error for the
case in which BERR is asserted after DSACK1/DSACK0. Exceptions are taken in both
cases. (Refer to Section 6 Exception Processing for details of bus error exception
processing.) When BERR is asserted during a read cycle that supplies an instruction to
the on-chip cache, the instruction in the cache is marked invalid.
When BERR is asserted after DSACK1/DSACK0, B E R R must be asserted within
parameter #48 (refer to Section 10 Electrical Characteristics) for purely asynchronous
operation, or it must be asserted and remain stable during the sample window, defined by
parameters #27A and #47B, around the next falling edge of the clock after
DSACK1/DSACK0 is recognized. If BERR is not stable at this time, the processor may
exhibit erratic behavior. In this case, data may be present on the bus, but may not be
valid. This sequence may be used by systems that have memory error detection and
correction logic and by external cache memories.
5.5.2 Retry Operation
When BERR and HALT are asserted simultaneously by an external device during a bus
cycle, the processor enters the retry sequence. A delayed retry similar to the delayed
BERR signal described previously can also occur.
The processor terminates the bus cycle, negates the control signals (AS, DS, R/W, SIZ1,
SIZ0, RMC, and, for the MC68020 only, ECS and OCS), and does not begin another bus
cycle until the BERR and HALT signals have been negated by external logic. After a
synchronization delay, the processor retries the previous cycle using the same access
information (address, function code, size, etc.) The BERR signal should be negated before
S2 of the read cycle to ensure correct operation of the retried cycle. Figure 5-40 shows a
late retry operation of a cycle.
The processor retries any read or write cycle of a read-modify-write operation separately;
RMC remains asserted during the entire retry sequence.
Asserting BR along with BERR and HALT provides a relinquish and retry operation. The
MC68020/EC020 does not relinquish the bus during a read-modify-write operation. Any
device that requires the processor to give up the bus and retry a bus cycle during a read-
modify-write cycle must assert BERR and BR only (HALT must not be included). The bus
error handler software should examine the read-modify-write bit in the special status word
(refer to Section 6 Exception Processing) and take the appropriate action to resolve this
type of fault when it occurs.
5-56
1. DSACK1/DSACK0 and HALT are negated and BERR is asserted.
2. HALT and BERR are negated and DSACK1/DSACK0 is asserted. BERR is then
3. BERR and HALT are asserted (see 5.5.2 Retry Operation).
asserted within one clock cycle (HALT remains negated).
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USER’S MANUAL
Go to: www.freescale.com
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