MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 203

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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The value in the main processor scanPC at the time this primitive is received is saved in
the scanPC field of the postinstruction exception stack frame. The value of the PC saved
is the F-line operation word address of the coprocessor instruction during which the
primitive is received.
When the MC68020/EC020 receives the take postinstruction exception primitive, it
assumes that the coprocessor either completed or aborted the instruction with an
exception. If the exception handler does not modify the stack frame, the MC68020/EC020
returns from the exception handler to begin execution at the location specified by the
scanPC field of the stack frame. This location should be the address of the next instruction
to be executed.
The coprocessor uses this primitive to request exception processing when it completes or
aborts an instruction while the main processor is awaiting a normal response. For a
general category instruction, the response is a release; for a conditional category
instruction, it is an evaluated true/false condition indicator. Thus, the operation of the
MC68020/EC020 in response to this primitive is compatible with standard M68000 family
instruction related exception processing (for example, the divide-by-zero exception).
7.5 EXCEPTIONS
Various exception conditions related to the execution of coprocessor instructions may
occur. Whether an exception is detected by the main processor or by the coprocessor, the
main processor coordinates and performs exception processing. Servicing these
coprocessor-related exceptions is an extension of the protocol used to service standard
M68000 family exceptions. That is, when either the main processor detects an exception
or is signaled by the coprocessor that an exception condition has occurred, the main
processor proceeds with exception processing as described in Section 6 Exception
Processing.
7.5.1 Coprocessor-Detected Exceptions
Coprocessor interface exceptions that the coprocessor detects, as well as those that the
main processor detects, are usually classified as coprocessor-detected exceptions.
Coprocessor-detected exceptions can occur during M68000 coprocessor interface
operations, internal operations, or other system-related operations of the coprocessor.
Most coprocessor-detected exceptions are signaled to the main processor through the use
of one of the three take exception primitives defined for the M68000 coprocessor
interface. The main processor responds to these primitives as described in 7.4.18 Take
Preinstruction Exception Primitive, 7.4.19 Take Midinstruction Exception Primitive,
and 7.4.20 Take Postinstruction Exception Primitive. However, not all coprocessor-
detected exceptions are signaled by response primitives. Coprocessor-detected format
errors during the cpSAVE or cpRESTORE instruction are signaled to the main processor
using the invalid format word described in 7.2.3.2.3 Invalid Format Words.
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