MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 158

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

To improve the efficiency of operand transfers between memory and the coprocessor, a
coprocessor that requires a relatively high amount of bus bandwidth or has special bus
requirements can be implemented as a DMA coprocessor. The DMA coprocessor
provides all control, address, and data signals necessary to request and obtain the bus
and then performs DMA transfers using the bus. DMA coprocessors, however, must still
act as bus slaves when they require information or services of the main processor using
the M68000 coprocessor interface protocol.
7.1.4.2 PROCESSOR-COPROCESSOR INTERFACE. Figure 7-2 is a block diagram of
the signals involved in an asynchronous non-DMA M68000 coprocessor interface. Since
the CpID on signals A15–A13 of the address bus is used with other address signals to
select the coprocessor, the system designer can use several coprocessors of the same
type and assign a unique CpID to each one.
The MC68020/EC020 accesses the registers in the CIR set using standard asynchronous
bus cycles. Thus, the bus interface implemented by a coprocessor for its interface register
set must satisfy the MC68020/EC020 address, data, and control signal timing. The
MC68020/EC020 bus operation is described in detail in Section 5 Bus Operation.
MOTOROLA
FC2–FC0 = 111
A19–A16 = 0010
A15–A13 = xxx
A4–A1 = rrrr
*
Chip select logic may be integrated into the coprocessor.
Address lines not specified above are "0" during coprocessor access.
MAIN PROCESSOR
MC68020/EC020
Figure 7-2. Asynchronous Non-DMA M68000
CPU SPACE CYCLE
COPROCESSOR ACCESS IN CPU SPACE
COPROCESSOR IDENTIFICATION
COPROCESSOR INFERFACE REGISTER SELECTOR
Freescale Semiconductor, Inc.
Coprocessor Interface Signal Usage
For More Information On This Product,
A4–A1
DS
R/W
AS
FC2–FC0
A19–A13
D31–D0
Go to: www.freescale.com
M68020 USER’S MANUAL
COPROCESSOR
DECODE
LOGIC
*
DSACK1 / DSACK0
CS
ASYNCHRONOUS
COPROCESSOR
INTERFACE
LOGIC
BUS
7- 5