MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 67

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment
The combination of operand size, operand alignment, and port size determine the number
of bus cycles required to perform a particular memory access. Table 5-6 lists the number
of bus cycles required for different operand sizes to different port sizes with all possible
alignment conditions for read/write cycles.
Table 5-6 reveals that bus cycle throughput is significantly affected by port size and
alignment. The MC68020/EC020 system designer and programmer should be aware of
and account for these effects, particularly in time-critical applications.
5-20
31
D31
OP0
MSB
OP1
XXX
*
Instruction prefetches are always two words from a long-word boundary
Instruction
Byte Operand
Word Operand
Long-Word Operand
Figure 5-17. Misaligned Long-Word Operand Read
LONG-WORD OPERAND (REGISTER)
Operand Size
OP1
UMB
OP2
Table 5-6. Memory Alignment and Port Size
XXX
LONG-WORD MEMORY
*
Freescale Semiconductor, Inc.
Influence on Read/Write Bus Cycles
DATA BUS
For More Information On This Product,
from Long-Word Port Example
M68020 USER’S MANUAL
LMB
XXX
OP3
OP2
Go to: www.freescale.com
1:2:4
1:1:1
1:1:2
1:2:4
(Data Port Size = 32 Bits:16 Bits:8 Bits)
00
Number of Bus Cycles
OP0
LSB
XXX
OP3
1:1:1
1:2:2
2:3:4
N/A
01
A1, A0
D0
0
SIZ1 SIZ0 A2
0
1
1:1:1
1:1:2
2:2:4
N/A
10
MC68020/EC020
0
1
0
1
A1
1
0
1:1:1
2:2:2
2:3:4
N/A
11
A0
1
0
MEMORY CONTROL
DSACK1
L
L
MOTOROLA
DSACK0
L
L