MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 151

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
corresponding fault bit (FB or FC) is cleared, the associated prefetch cycle may or may
not be run by the RTE instruction (depending on whether the stage is required).
If a fault occurs when the RTE instruction attempts to rerun the bus cycle(s), the processor
creates a new stack frame on the supervisor stack after deallocating the previous frame,
and address error or bus error exception processing starts in the normal manner.
The read-modify-write operations of the MC68020/EC020 can also be completed by the
RTE instruction that terminates the handler routine. The rerun operation, executed by the
RTE instruction with the DF bit of the SSW set, reruns the entire instruction. If the cause of
the error has been corrected, the handler does not need to emulate the instruction but can
leave the DF bit set and execute the RTE instruction.
6.3 COPROCESSOR CONSIDERATIONS
Exception handler programmers should consider carefully whether to save and restore the
context of a coprocessor at the beginning and end of handler routines for exceptions that
can occur during the execution of a coprocessor instruction (i.e., bus errors, interrupts,
and coprocessor-related exceptions). The nature of the coprocessor and the exception
handler routine determines whether or not saving the state of one or more coprocessors
with the cpSAVE and cpRESTORE instructions is required. If the coprocessor allows
multiple coprocessor instructions to be executed concurrently, it may require its state to be
saved and restored for all coprocessor-generated exceptions, regardless of whether or not
the coprocessor is accessed during the handler routine. The MC68882 floating-point
coprocessor is an example of this type of coprocessor. On the other hand, the MC68881
floating-point coprocessor requires FSAVE and FRESTORE instructions within an
exception handler routine only if the exception handler itself uses the coprocessor.
6.4 EXCEPTION STACK FRAME FORMATS
The MC68020/EC020 provides six different stack frames for exception processing. The
set of frames includes the normal four- and six-word stack frames, the four-word
throwaway stack frame, the coprocessor midinstruction stack frame, and the short and
long bus fault stack frames.
When the MC68020/EC020 writes or reads a stack frame, it uses long-word operand
transfers wherever possible. Using a long-word-aligned stack pointer with memory that is
on a 32-bit port greatly enhances exception processing performance. The processor does
not necessarily read or write the stack frame data in sequential order.
The system software should not depend on a particular exception generating a particular
stack frame. For compatibility with future devices, the software should be able to handle
any type of stack frame for any type of exception.
Table 6-5 summarizes the stack frames defined for the MC68020/EC020.
6-26
M68020 USER’S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com