CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 26

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

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5.2.5 Internal Digital Loopback
5.2.6 Auto-Mute
5.2.7 High-Pass Filter and DC Offset Calibration
Double-Speed
Quad-Speed
In Control Port Mode, the CS4270 supports an internal digital loopback mode in which the output of the
ADC is routed to the input of the DAC. This mode may be activated by setting the Digital Loopback bit in
the ADC & DAC Ctrl register (04h).
When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270.
Any changes made to the DAC_DIF(4:3) bits while the Digital Loopback bit is set will have no impact on
operation until the Digital Loopback bit is released, at which time the Digital Interface Format of the DAC
will operate according to the format selected in the DAC_DIF(4:3) bits. While the Digital Loopback bit is
set, data will be present on the SDOUT pin in the format selected in the ADC_DIF(0) bit in register 04h.
The Auto-Mute function is controlled by the status of the Auto Mute bit in the Mute register. When set, the
DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single
sample of non-static data will release the mute. Detection and muting are done independently for each
channel. The common mode on the output will be retained and the Mute Control pin for that channel will
become active during the mute period. The muting function is affected, similar to volume control changes,
by the Soft and ZeroCross bits in the Transition and Control register. The Auto Mute bit is set by default.
The input circuitry driving the CS4270 may generate a small DC offset into the A/D converter. The CS4270
includes a high-pass filter after the decimator to remove any DC offset which could result in recording a
DC level, possibly yielding "clicks" when switching between devices in a multichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. The high-pass filter can be enabled if the hpf_freeze bit is set during normal operation, the current
value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be sub-
tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration
by:
1. Running the CS4270 with the high-pass filter enabled until the filter settles. See the Digital Filter
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4270.
Characteristics for filter settling time.
128
192
256
384
512
128
192
256
64
96
Table 5. Clock Ratios - Control Port Mode (Continued)
32, 48, 64
32, 48, 64
32, 48, 64
32, 48, 64
32, 64
48, 64
32, 64
48, 64
32, 64
32
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
1
0
CS4270
DS686PP1
0
1
0
1
0
0
1
0
1
0