CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 38

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

38
8.5
8.5.1 DAC Single Volume (Bit 7)
8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5)
8.5.3 Invert Signal Polarity (Bits 4:1)
DAC Single
Volume
7
Transition Control - Address 05h
Function:
The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by
the A Channel Volume Control Byte (07h) and the B Channel Byte (08h) is ignored when this function is
enabled. Volume and muting functions are affected by the Soft Ramp and ZeroCross functions below.
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See
Function:
When set, this bit activates an inversion of the signal polarity for the appropriate channel. This is useful if
a board layout error has occurred or in other situations where a 180 degree phase shift is desirable.
Table 12 on page
soft_dac
6
Soft
0
0
1
1
zc_dac
Table 12. Soft Cross or Zero Cross Mode Selection
Table 9 on page
38.
5
ZeroCross
0
1
0
1
ADC ch B
invert
4
36.
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled
(default)
Table 9 on page
ADC ch A
invert
3
Mode
DAC ch B
36.
invert
2
DAC ch A
invert
1
CS4270
De-emph
DS686PP1
0