CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 36

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

36
8.3
8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4)
8.3.2 Ratio Select (Bits 3:1)
8.3.3 Popguard Disable (Bit 0)
8.4
8.4.1 ADC HPF Freeze A (Bit 7)
ADC HPF
Reserved
Freeze A
7
7
Mode Control - Address 03h
ADC and DAC Control - Address 04h
Function:
In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Control
Port Slave Mode, the CS4270 auto-detects speed mode.
Function:
These bits are used to select the clocking ratios.
Function:
Disables Popguard when set. Popguard is enabled by default.
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC
offset value will be frozen and continuously subtracted from the conversion result.
Pass Filter and DC Offset Calibration” on page
MCLK freq<2>
FM_&_M/S_
Mode1
Reserved
ADC HPF
0
0
1
1
Freeze B
0
0
0
0
1
6
6
FM_&_M/S_
Mode0
FM_&_M/S_
0
1
0
1
Loopback
Mode1
Digital
MCLK freq<1>
5
5
Single-Speed Mode: 4 to 54 kHz sample rates
Double-Speed Mode: 50 to 108 kHz sample rates
Quad-Speed Mode: 100 to 216 kHz sample rates
Slave Mode (default)
Table 9. MCLK Divider Configuration
Table 8. Functional Mode Selection
0
0
1
1
0
FM_&_M/S_
DAC_DIF1
Mode0
4
4
26.
MCLK freq<2> MCLK freq<1> MCLK freq<0>
DAC_DIF0
MCLK freq<0>
3
3
0
1
0
1
0
Mode
Reserved
2
2
Divide by 1 (default)
Divide by 1.5
Divide by 2
Divide by 3
Divide by 4
Reserved
Mode
1
1
Section 5.2.7 “High-
ADC_DIF0
CS4270
Popguard
DS686PP1
Disable
0
0