CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 37

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

DS686PP1
8.4.2 ADC HPF Freeze B (Bit 6)
8.4.3 Digital Loopback (Bit 5)
8.4.4 DAC Digital Interface Format (Bits 4:3)
8.4.5 ADC Digital Interface Format (Bit 0)
DAC_DIF1 DAC_DIF0
ADC_DIF
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC
offset value will be frozen and continuously subtracted from the conversion result.
Pass Filter and DC Offset Calibration” on page
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
Section 5.2.5 “Internal Digital Loopback” on page
Function:
The DAC Digital Interface Format and the options are detailed in
Function:
The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Digital
Interface Format. The options are detailed in
0
1
0
0
1
1
0
1
1
0
Left-Justified, up to 24-bit data (default)
Left-Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Table 10. DAC Digital Interface Formats
Table 11. ADC Digital Interface Formats
Description
Right-Justified, 16-bit Data
Right-Justified, 24-bit Data
I²S, up to 24-bit data
Description
Table 11
26.
26.
and may be seen in
Table 10
Format
0
1
Format
0
1
2
3
and Figures
Figures 9
Section 5.2.7 “High-
and 10.
Figure
Figure
9
10
11
11
10
9
through 11.
9
CS4270
37