CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 32

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

32
6. CONTROL PORT INTERFACE
The Control Port is used to load all the internal settings of the CS4270. The operation of the Control Port may be
completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the Control
Port pins should remain static if no operation is required.
The Control Port has 2 modes: SPI and I²C, with the CS4270 operating as a slave to control messages in both
modes. If I²C operation is desired, AD0/CS should be tied to VLC or DGND. If the CS4270 ever detects a high to
low transition on AD0/CS after power-up, SPI Mode will be selected.
Upon release of the RST pin, the CS4270 will wait approximately 10 ms before it begins its start-up sequence. The
part defaults to Stand-Alone Mode, in which all operational modes are controlled as described in
page
Mode and all operational modes are controlled by the Control Port registers. If system requirements do not allow
writing to the Control Port immediately following the release of RST, the SDIN line should be held at logic “0” until
the proper serial mode can be selected.
6.1
22. If the user initiates communication to the part through the SPI or I²C interface, the part enters Control-Port
SPI™ Mode
In SPI Mode, CS is the CS4270 chip select signal, CCLK is the Control Port bit clock, CDIN is the input data
line from the microcontroller and the chip address is 1001111. All control signals are inputs and data is
clocked in on the rising edge of CCLK.
Figure 21
7 bits on CDIN form the chip address, and must be 1001111. The eighth bit is a read/write indicator (R/W),
which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the
address of the register that is to be updated. The next 8 bits are the data which will be placed into the register
designated by the MAP. See
The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the
MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte
is written, allowing block writes to successive registers.
shows the operation of the Control Port in SPI Mode. To write to a register, bring CS low. The first
CS
CCLK
CDIN
Figure 21. Control Port Timing, SPI Mode
Table 9 on page
MAP = Memory Address Pointer
ADDRESS
1001111
CHIP
R/W
36.
MAP
MSB
byte 1
DATA
byte n
LSB
Section 5.1 on
CS4270
DS686PP1