SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 106

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

SAB 82532/SAF 82532
Operational Description
ASYNC: The transmission of character(s) can be started by issuing a XF command via
the CMDR register. The ESCC2 will repeatedly request for the next data block by means
of a XPR interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a
32-byte pool is accessible to the CPU. Transmission may be aborted per software
(CMDR:XRES).
BISYNC: The transmission of a block can be started by issuing a XF command via the
CMDR register. Further handling of data transmission with respect to preamble
transmission and command XME is similar to HDLC/SDLC mode. After XME command
has been issued, the block is finished by appending the internally generated CRC if
enabled (refer to description of register CCR3).
In case no more data is available in the XFIFO prior to the arrival of XME, the
transmission of the block is terminated with IDLE and the CPU is notified per interrupt
(ISR1:XDU). The block may also be aborted per software (CMDR:XRES). The data
transmission flow, from the CPU’s point of view, is outlined in figure 46.
Figure 46
Interrupt Driven Data Transmission (Flow Diagram)
Semiconductor Group
106
07.96