SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 53

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

5.2
When operating in the auto mode, the ESCC2 offers a high degree of protocol support.
In addition to address recognition, the ESCC2 autonomously processes all (numbered)
S- and I-frames (prerequisite window size 1) with either normal or extended control field
format (modulo-8 or modulo-128 sequence numbers – selectable via RAH2 register).
The following functions will be performed:
– updating of transmit and receive counter
– evaluation of transmit and receive counter
– processing of S commands
– flow control with RR/RNR
– generation of responses
– recognition of protocol errors
– transmission of S commands, if acknowledgement is not received
– continuous status query of remote station after RNR has been received
– programmable timer/repeater functions.
In addition, all unnumbered frames are forwarded directly to the processor. The logical
link can be initialized by software at any time (Reset HDLC Receiver, RHR command).
Additional logical connections can be operated in parallel by software.
5.2.1
Initially (i.e. after RESET), the LAP controllers of the two serial channels are configured
to function as a combined (primary/secondary) station, where they autonomously
perform a subset of the balanced X.25 LAPB/ISDN LAPD protocol.
Reception of Frames
The logical processing of received S-frames is performed by the ESCC2 without
interrupting the CPU. The CPU is merely informed by interrupt of status changes in the
remote station (receiver ready / receiver not ready) and protocol errors (unacceptable
N(R), or S-frame with I field).
I-frames are also processed autonomously and checked for protocol errors. The I-frame
will not be accepted in the case of sequence errors (no interrupt is forwarded to the
CPU), but is immediately confirmed by an S-response. If the CPU sets the ESCC2 into
a ‘receive not ready’ status, an I-frame will not be accepted (no interrupt) and an RNR
response is transmitted. U-frames are always stored in the RFIFO and forwarded directly
to the CPU. The logical sequence and the reception of a frame in auto mode is illustrated
in figure 24.
Note: The state variables N(S), N(R) are evaluated within the window size 1, i.e. the
Semiconductor Group
ESCC2 checks only the least significant bit of the receive and transmit counter
regardless of the selected modulo count.
Procedural Support (layer-2 functions)
Full-Duplex LAPB/LAPD Operation
53
SAB 82532/SAF 82532
HDLC/SDLC Serial Mode
07.96