SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 66

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
5.4.7
The ESCC2 offers the possibility to supervise the maximum length of received frames
and to terminate data reception in case this length is exceeded.
This feature is controlled via the special Receive Length Check Register (RLCR).
The function is enabled by setting the RC (Receive Check) bit in RLCR and
programming the maximum frame length via bits RL6 … RL0. The maximum receive
length can be determined as a multiple of 32-byte blocks as follows:
MAX_LENGTH = (RL + 1)
where RL is the value written to RL6 … RL0.
All frames exceeding this length are treated as if they had been aborted by the remote
station, i.e. the CPU is informed via an
– RME interrupt, and the
– RAB bit in RSTA register is set.
To distinguish this from the case where an abort sequence is indeed received (sent by
the remote station), the receive byte count registers RBCH, RBCL will contain a value
exceeding the maximum receive length (via RL6 … RL0) by one or two bytes.
5.4.8
Similar to the zero bit insertion (bit stuffing) mechanism, as defined by the HDLC
protocol, the ESCC2 offers a completely new feature of inserting/deleting a one after
seven consecutive ‘zeros’ in the transmit/receive data stream, if the serial channel is
operating in a bus configuration. This method is useful if clock recovery is to be
performed by DPLL.
Since only NRZ data encoding is supported in a bus configuration, there are possibly
long sequences without edges in the receive data stream in case of successive ‘0’s
received, and the DPLL may lose synchronization.
Using the one bit insertion feature by setting the OIN bit in the CCR1 register, however,
it is guaranteed that at least after
– 5 consecutive ‘1’s a ‘0’ will appear (bit stuffing), and after
– 7 consecutive ‘0’s a ‘1’ will appear (one insertion)
and thus a correct function of the DPLL is ensured.
Note: As with the bit stuffing, the ‘one insertion’ is fully transparent to the user, but it is
not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary
systems using circuits that also implement this function, such as the
SAB 82525/SAB 82526.
Receive Length Check Feature
One Bit Insertion
32
66
SAB 82532/SAF 82532
HDLC/SDLC Serial Mode
07.96