SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 48

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

SAB 82532/SAF 82532
DMA Interface
4
DMA Interface
The ESCC2 comprises a 4-channel DMA interface for fast and efficient data transfers.
For both serial channels, a separate DMA Request output for transmit (DRT) and receive
direction (DRR) as well as a DMA Acknowledgement (DACK) input is provided.
The ESCC2 activates the DMA Request line as long as data transfers are needed
from/to the specific FIFO (level triggered demand transfer mode of DMA controller).
It is the responsibility of the DMA controller to perform the correct amount of bus cycles.
Either read cycles will be performed if the DMA transfer has been requested from the
receiver, or write cycles if DMA has been requested from the transmitter. If the DMA
controller provides a DMA acknowledge signal (input to the ESCC2’s DACK pin), each
bus cycle implicitly selects the top of the specific FIFO and neither address (via
A0 … A6) nor chip select need to be supplied (I/O to memory transfers). If no DACK
signal is supplied, normal read/write operations (with addresses) must be performed
(memory to memory transfers). The ESCC2 deactivates the DMA Request line
immediately after the last read/write cycle of the data transfer has started.
As a very useful feature for single cycle DMA transfers, optional inversion of the
functions of read/write control lines is implemented. If programmed via register CCR2
– RD and WR are exchanged in Intel bus interface mode,
– R/W is inverted in Motorola bus interface mode
while DACK is active. This allows easy connection to DMA controllers without dedicated
I/O control lines as shown in figure 21.
Figure 21
DMA Interfacing by Using Invert Mode
Semiconductor Group
48
07.96