PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 129

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.3
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>)
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0,etc.) clear the prescaler count.
TABLE 11-1:
© 2006 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
INTCON2
T0CON
TRISA
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.
Note 1:
Note:
Name
Prescaler
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Timer0 Register Low Byte
Timer0 Register High Byte
GIE/GIEH PEIE/GIEL TMR0IE
TMR0ON
RBPU
Bit 7
which
REGISTERS ASSOCIATED WITH TIMER0
—
determine
TRISA6
INTEDG0 INTEDG1 INTEDG2
T08BIT
Bit 6
(1)
the
TRISA5
T0CS
Bit 5
PIC18F2455/2550/4455/4550
prescaler
Preliminary
TRISA4
INT0IE
T0SE
Bit 4
TRISA3
11.3.1
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before re-
enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
RBIE
Bit 3
PSA
—
Timer0 Interrupt
TMR0IF
TMR0IP
TRISA2
T0PS2
SWITCHING PRESCALER
ASSIGNMENT
Bit 2
TRISA1
INT0IF
T0PS1
Bit 1
—
TRISA0
T0PS0
RBIF
RBIP
Bit 0
DS39632C-page 127
on page
Values
Reset
52
52
51
51
52
54