PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 172

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PIC18F4550-I/P

Manufacturer Part Number
PIC18F4550-I/P
Description
40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4550-I/P

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC18F2455/2550/4455/4550
17.2.5
The USB Address register contains the unique USB
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received,
indicated by URSTIF, or when a Reset is received from
the microcontroller. The USB address must be written
by the microcontroller during the USB setup phase
(enumeration) as part of the Microchip USB firmware
support.
17.2.6
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame
isochronous transfers.
17.3
USB data moves between the microcontroller core and
the SIE through a memory space known as the USB
RAM. This is a special dual port memory that is
mapped into the normal data memory space in Banks 4
through 7 (400h to 7FFh) for a total of 1 Kbyte
(Figure 17-5).
Bank 4 (400h through 4FFh) is used specifically for
endpoint buffer control, while Banks 5 through 7 are
available for USB data. Depending on the type of
buffering being used, all but 8 bytes of Bank 4 may also
be available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 17.4.1.1 “Buffer
Ownership”.
DS39632C-page 170
Number
USB RAM
USB ADDRESS REGISTER
(UADDR)
USB FRAME NUMBER REGISTERS
(UFRMH:UFRML)
register
is
primarily
used
Preliminary
for
FIGURE 17-5:
(USB RAM)
Banks 4
Banks 8
Banks 0
Bank15
to 14
to 7
to 3
USB Data or User Data
Buffer Descriptors,
IMPLEMENTATION OF
USB RAM IN DATA
MEMORY SPACE
© 2006 Microchip Technology Inc.
USB Data or
User Data
User Data
Unused
SFRs
000h
3FFh
400h
4FFh
500h
7FFh
800h
F00h
F60h
FFFh

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