PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet - Page 34

• Manufacturer Part Number: PIC12F683-I/SN
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-I/SN

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin SOIC-N
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F683
REGISTER 4-2:
4.2
Every GPIO pin
interrupt-on-change option and a weak pull-up option.
GP0 has an Ultra Low-Power Wake-up option. The
next three sections describe these functions.
4.2.1
The ANSEL register is used to configure the Input
mode of an I/O pin to analog. Setting the appropriate
ANSEL bit high will cause all digital reads on the pin to
be read as ‘0’ and allow analog functions on the pin to
operate correctly.
The state of the ANSEL bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
4.2.2
Each of the GPIO pins, except GP3, has an individually
configurable internal weak pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 4-4.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit of the
OPTION register). A weak pull-up is automatically
enabled for GP3 when configured as MCLR and
disabled when GP3 is an I/O. There is no software
control of the MCLR pull-up.
DS41211C-page 32
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5:4
bit 3
bit 2:0
Note 1:
U-0
—
2:
3:
Additional Pin Functions
TRISIO<3> always reads ‘1’.
TRISIO<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
TRISIO<5> always reads ‘1’ in RC and RCIO and EC modes.
ANSEL REGISTER
WEAK PULL-UPS
Unimplemented: Read as ‘0’
TRISIO<5:4>: GPIO Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
TRISIO<3>: GPIO Tri-State Control bit
Input only
TRISIO<2:0>: GPIO Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
U-0
on
—
TRISIO GPIO TRI-STATE REGISTER
the
W = Writable bit
‘1’ = Bit is set
PIC12F683 has
TRISIO5
R/W-1
(2,3)
TRISIO4
R/W-1
an
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRISIO3
4.2.3
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOCx enable or
disable the interrupt function for each pin. Refer to
Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set the GPIO Change Interrupt Flag bit
(GPIF) in the INTCON register (Register 3-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor
Brown-out Reset. After these resets, the GPIF flag will
continue to be set if a mismatch is present.
R-1
Note:
Any read or write of GPIO. This will end the
mismatch condition, then,
Clear the flag bit GPIF.
(1)
INTERRUPT-ON-CHANGE
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
TRISIO2
R/W-1
© 2006 Microchip Technology Inc.
x = Bit is unknown
TRISIO1
R/W-1
TRISIO0
R/W-1
bit 0