PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet - Page 59

• Manufacturer Part Number: PIC12F683-I/SN
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-I/SN

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin SOIC-N
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.9
This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the
CMCON1 register will enable Timer1 to increment
based on the output of the comparator. This requires
that Timer1 is on and gating is enabled. See
Section 6.0 “Timer1 Module with Gate Control” for
details.
It is recommended to synchronize the comparator with
Timer1 by setting the CMSYNC bit when the
comparator is used as the Timer1 gate source. This
ensures Timer1 does not miss an increment if the
comparator changes during an increment.
REGISTER 8-2:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
Note 1:
U-0
—
2:
Comparator Gating Timer1
Refer to Section 6.6 “Timer1 Gate”.
Refer to Figure 8-2.
Unimplemented: Read as ‘0’
T1GSS: Timer1 Gate Source Select bit
1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input)
0 = Timer 1 Gate Source is comparator output
CMSYNC: Comparator Output Synchronization bit
1 = Output is synchronized with falling edge of Timer1 clock
0 = Output is asynchronous
U-0
—
CMCON1: COMPARATOR CONFIGURATION REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
8.10
The comparator output can be synchronized with
Timer1 by setting the CMSYNC bit of the CMCON1
register. When enabled, the comparator output is
latched on the falling edge of the Timer1 clock source.
If a prescaler is used with Timer1, the comparator
output is latched after the prescaling function. To
prevent a race condition, the comparator output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. See the Comparator Block Diagram (Figure 8-
2) and the Timer1 Block Diagram (Figure 6-1) for more
information.
U-0
—
(2)
Synchronizing Comparator Output
to Timer1
U-0
—
x = Bit is unknown
PIC12F683
T1GSS
R/W-1
DS41211C-page 57
CMSYNC
R/W-0
bit 0