PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet - Page 95

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PIC12F683-I/SN

Manufacturer Part Number
PIC12F683-I/SN
Description
8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC12F683-I/SN

A/d Inputs
4-Channel, 10-Bit
Comparators
1
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
5
Memory Type
Flash
Number Of Bits
8
Package Type
8-pin SOIC-N
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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0
12.4.2
An overflow (FFh
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing the T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
FIGURE 12-7:
© 2006 Microchip Technology Inc.
TIMER0 INTERRUPT
IOC-GP0
IOC-GP1
IOC-GP2
IOC-GP3
IOC-GP4
IOC-GP5
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
OSFIF
OSFIE
CMIF
CMIE
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
ADIF
ADIE
EEIF
EEIE
00h) in the TMR0 register will set
INTERRUPT LOGIC
GPIF
GPIE
INTF
INTE
PEIE
T0IF
T0IE
GIE
12.4.3
An input change on GPIO change sets the GPIF bit of
the
enabled/disabled by setting/clearing the GPIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
Note:
INTCON
GPIO INTERRUPT
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
register.
Wake-up (If in Sleep mode)
PIC12F683
The
Interrupt to CPU
interrupt
DS41211C-page 93
can
be

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