PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 160
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PEF82912FV14XP
Manufacturer Part Number
PEF82912FV14XP
Description
Manufacturer
Lantiq
Datasheet
1.PEF82912FV14XP.pdf
(240 pages)
Specifications of PEF82912FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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ISTAU
MASKU
FW_
VERSION
*) read back function for test use
Note: Registers, which are denoted as ‘reserved‘, may not be accessed by the µC,
4.4
The following U-transceiver registers are reset during deactivation or with software reset:
Table 34
Register
EOCR
EOCW
M4R
M4W
M56R
M56W
TEST
LOOP
Data Sheet
neither for read nor for write operations.
Reset of U-Transceiver Functions During Deactivation or with
C/I-Code RESET
MLT
MLT
Reset of U-Transceiver Functions During Deactivation or with C/I-
Code RESET
Reset to
0FFF
0100
BE
BE
1F
FF
CI
CI
H
H
H
H
H
H
FEBE/
FEBE/
NEBE
NEBE
FW Version Number
Affected Bits
all bits
all bits
all bits
all bits
all bits are reset besides MS2 and MS1
all bits
only bit CCRC is reset
only the bits LBBD, LB2 and LB1 are reset
M56
M56
reserved
reserved
146
M4
M4
EOC
EOC
6ms
6ms
12ms
12ms
Register Description
PEF 82912/82913
7E
7A
7B
7C
7D
7F
H
H
H
H
H
H
-
R*/W FF
2001-03-30
R
R
00
6x
H
H
H
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