PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 201
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PEF82912FV14XP
Manufacturer Part Number
PEF82912FV14XP
Description
Manufacturer
Lantiq
Datasheet
1.PEF82912FV14XP.pdf
(240 pages)
Specifications of PEF82912FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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NEBE
M61,
M52, M51
FEBE
4.11.10
Via the M56 bit Write register, the M5 and M6 bits of the next available superframe can
be set. The value is latched and transmitted as long as a new value is set or the function
is disabled. The FEBE bit can only be set and controlled externally if OPMODE.FEBE is
set to ‘1’.
M56W
Reset Value:
M61,
M52, M51
FEBE
4.11.11
Via the U-transceiver C/I code Read register a microcontroller can access the C/I code
that is output from the state machine.
Data Sheet
7
1
M56W - M56 Write Register
UCIR - C/I Code Read Register
Near-End Block Error
0 =
1 =
Received Spare Bits of last U superframe (M51, M52 and M61 have no
effect on the Q-SMINT I ).
Far-End Block Error
0 =
1 =
Transmitted Spare Bits to next U superframe (M51, M52 and M61 have no
effect on the Q-SMINT I.
Far-End Block Error
0 =
1 =
FF
6
1
Near-End Block Error has occurred
no Near-End Block Error has occurred
Far-End Block Error has occurred
no Far-End Block Error has occurred
H
Far-End Block Error has occurred
no Far-End Block Error has occurred
5
1
4
1
write
187
M61
3
M52
2
Register Description
PEF 82912/82913
M51
Address:
1
2001-03-30
FEBE
0
6C
H
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