PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 175

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MOS
Note: A read of the ISTA register clears only the WOV interrupt. The other interrupts are
4.8.2
MASK
Value after reset: FF
Bit 7..0
Each interrupt source in the ISTA register can be selectively masked by setting the
corresponding bit in MASK to ‘1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ‘0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
Data Sheet
cleared by reading the corresponding status register.
mask bit in MASK is active, but no interrupt is generated.
U
7
MASK - Mask Register
0 =
1 =
MONITOR Status
0 =
1 =
0 =
Mask bits
0 =
1 =
ST
inactive
inactive
A change in the MONITOR Status Register (MOSR) has occurred.
inactive
An interrupt was generated by the S-transceiver. Read the ISTAS
register.
Interrupt is not masked
Interrupt is masked
H
CIC
1
write
161
WOV
S
Register Description
PEF 82912/82913
MOS
Address:
2001-03-30
0
1
3C
H