PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 29

PEF82912FV14XP

Manufacturer Part Number
PEF82912FV14XP
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF82912FV14XP

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
Figure 4
Alternatively, the Q-SMINT I can be controlled via
Data Sheet
b) the IOM -2 Interface
- Access of on-chip registers via the Monitor channel with Header/Address/Data
format (Device is Monitor slave)
- Activation/Deactivation control of U- and S-transceiver via the C/I channels CI0
and CI1
- TIC bus is transparent on IOM -2-interface and is used for D-channel arbitration
between S-transceiver and off-chip HDLC controllers.
e.g. SLICOFI-2
IOM-2 Slave
Control via µP Interface
S
IOM -2
MON
C/I1
15
Mon
µc - Interface
C/I0
C/I
µc
iommaster.vsd
Register
PEF 82912/82913
U
2001-03-30
Overview

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