PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 31
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PEF82912FV14XP
Manufacturer Part Number
PEF82912FV14XP
Description
Manufacturer
Lantiq
Datasheet
1.PEF82912FV14XP.pdf
(240 pages)
Specifications of PEF82912FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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2
2.1
The Q-SMINT I supports either a serial or a parallel microcontroller interface. For
applications where no controller is connected to the Q-SMINT I microcontroller
interface, register programming is done via the IOM -2 MONITOR channel from a
master device. In such applications the Q-SMINT I operates in the IOM -2 slave mode
(refer to the corresponding chapter of the IOM -2 MONITOR handler).
The interface selections are all done by pinstrapping. The possible interface selections
are listed in
released. For the pin levels stated in the tables the following is defined:
’High’:dynamic pin value which must be ’High’ when the pin level is evaluated
V
•
Table 4
Note: For a selected interface mode which does not require all pins (e.g. address pins)
The microcontroller interface also consists of a microcontroller clock generation at pin
MCLK, an interrupt request at pin INT, a reset input pin RST and a reset output pin
RSTO.
The interrupt request pin INT (open drain output) becomes active if the Q-SMINT I
requests an interrupt.
Data Sheet
(R/W)
’High’ ’High’
DD
WR
V
SS
, V
PINS
the unused pins must be tied to V
SS
:static ’High’ or ’Low’ level (tied to V
(DS)
V
RD
Functional Description
Microcontroller Interfaces
SS
Table
Interface Selection for the Q-SMINT I
Serial /Parallel
Interface
4. The selection pins are evaluated when the reset input RST is
Parallel
Serial
‘High’
’High’
V
CS
SS
PINS
DD
edge
ALE
.
17
V
V
V
V
DD
SS
SS
SS
DD
, V
SS
)
Serial Control Interface(SCI)
IOM -2 MONITOR Channel
Siemens/Intel Non-Mux
Siemens/Intel Mux
(Slave Mode)
Type/Mode
Functional Description
Interface
Motorola
PEF 82912/82913
2001-03-30
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