A000003 Arduino, A000003 Datasheet - Page 212

• Manufacturer Part Number: A000003
• Description: MCU, MPU & DSP Development Tools MINI
• Manufacturer: Arduino
• Series: -r
• Type: MCUr

Specifications of A000003

• Processor To Be Evaluated: Atmega328
• Processor Series: ATmega
• Data Bus Width: 8 bit
• Interface Type: USB, RS-232
• Operating Supply Voltage: 7 V to 9 V
• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega168

Figure 21-6. Typical Data Transmission
21.4
212
SDA
SCL
START
Multi-master Bus Systems, Arbitration and Synchronization
ATmega48/88/168
Addr MSB
1
2
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
• An algorithm must be implemented allowing only one of the masters to complete the
• Different masters may use different SCL frequencies. A scheme must be devised to
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the Master with the shortest high period. The low period of the combined clock is equal to
the low period of the Master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.
transmission. All other masters should cease transmission when they discover that they have
lost the selection process. This selection process is called arbitration. When a contending
master discovers that it has lost the arbitration process, it should immediately switch to Slave
mode to check whether it is being addressed by the winning master. The fact that multiple
masters have started transmission at the same time should not be detectable to the slaves,
that is, the data being transferred on the bus must not be corrupted.
synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
SLA+R/W
Addr LSB
7
R/W
8
ACK
9
Data MSB
1
2
Data Byte
7
Data LSB
8
ACK
9
2545S–AVR–07/10
STOP