DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 154

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 14-3:
14.6
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in an
Up/Down Count mode (see Figure 14-4).
The PWM compare output is driven to the active state
when the value of the Duty Cycle register matches the
value of PxTMR and the PWM time base is counting
downward (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upward (PTDIR = 0) and the value in the
PxTMR register matches the duty cycle value.
If the value in a particular Duty Cycle register is zero,
the output on the corresponding PWM pin is inactive for
the entire PWM period. In addition, the output on the
PWM pin is active for the entire PWM period if the value
in the Duty Cycle register is equal to the value held in
the PxTPER register.
FIGURE 14-4:
DS70283B-page 152
PxTPER
PxTPER
Cycle
Duty
0
0
Center-Aligned PWM
P
Value
Duty Cycle
X
TMR
Period/2
Period
EDGE-ALIGNED PWM
CENTER-ALIGNED PWM
Period
New Duty Cycle Latched
PTMR
Value
Preliminary
14.7
Three 16-bit Special Function Registers (PxDC1,
PxDC2, PxDC3) are used to specify duty cycle values
for the PWM module.
The value in each Duty Cycle register determines the
amount of time that the PWM output is active. The Duty
Cycle registers are 16 bits wide. The Least Significant
bit (LSb) of a Duty Cycle register determines whether
the PWM edge occurs in the beginning. Thus the PWM
resolution is effectively doubled.
14.7.1
The three PWM Duty Cycle registers are double-
buffered to allow glitchless updates of the PWM
outputs. For each duty cycle, there is a Duty Cycle
register that is accessible by the user application and a
second Duty Cycle register that holds the actual com-
pare value used in the present PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PxTPER
register occurs and PxTMR is reset. The contents of
the duty cycle buffers are automatically loaded into the
Duty Cycle registers when the PWM time base is
disabled (PTEN = 0) and the UDIS bit is cleared in
PWMxCON2.
When the PWM time base is in the Up/Down Count
mode, new duty cycle values are updated when the
value of the PxTMR register is zero, and the PWM time
base begins to count upward. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
When the PWM time base is in the Up/Down Count
mode with double updates, new duty cycle values are
updated when the value of the PxTMR register is zero,
and when the value of the PxTMR register matches the
value in the PxTPER register. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
PWM Duty Cycle Comparison
Units
DUTY CYCLE REGISTER BUFFERS
© 2007 Microchip Technology Inc.