DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 52

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
3.6.3
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. By incrementing the PC by 2 for each
program memory word, the lower 15 bits of data space
addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Although each data space address 8000h and higher
maps directly into a corresponding program memory
address (see Figure 3-9), only the lower 16 bits of the
FIGURE 3-9:
DS70283B-page 50
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
When CORCON<2> =
PSVPAG
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
02
PROGRAM SPACE VISIBILITY OPERATION
1
23
and EA<15> =
Program Space
15
1
:
0
0x000000
0x010000
0x018000
0x800000
Preliminary
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEAT loop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
• Execution upon re-entering the loop after an
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data, to execute in a
single cycle.
Note:
interrupt
interrupt is serviced
Data Space
PSV Area
PSV access is temporarily disabled during
table reads/writes.
0x0000
0x8000
0xFFFF
© 2007 Microchip Technology Inc.
and
...while the lower 15 bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
MOV.D instructions
Data EA<14:0>
1111’ or