DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 156

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.9.2
The PxDTCON2 SFR contains control bits that allow
the dead times to be assigned to each of the comple-
mentary outputs. Table 14-1 summarizes the function
of each dead-time selection control bit.
TABLE 14-1:
14.9.3
The amount of dead time provided by each dead-time
unit is selected by specifying the input clock prescaler
value and a 6-bit unsigned value. The amount of dead
time provided by each unit can be set independently.
Four input clock prescaler selections have been pro-
vided to allow a suitable range of dead times, based on
the device operating frequency. The clock prescaler
option can be selected independently for each of the
two dead-time values. The dead-time clock prescaler
values are selected using the DTAPS<1:0> and
DTBPS<1:0> control bits in the PxDTCON1 SFR. One
of four clock prescaler options (T
T
After the prescaler values are selected, the dead time
for each unit is adjusted by loading two 6-bit unsigned
values into the PxDTCON1 SFR.
The dead-time unit prescalers are cleared on the
following events:
• On a load of the down timer due to a duty cycle
• On a write to the PxDTCON1 or PxDTCON2
• On any device Reset.
DS70283B-page 154
DTS1A Selects PWMxL1/PWMxH1 active edge
DTS1I
DTS2A Selects PWMxL2/PWMxH2 active edge
DTS2I
DTS3A Selects PWMxL3/PWMxH3 active edge
DTS3I
CY
comparison edge event.
registers.
Note:
Bit
) can be selected for each of the dead-time values.
dead time.
Selects PWMxL1/PWMxH1 inactive edge
dead time.
dead time.
Selects PWMxL2/PWMxH2 inactive edge
dead time.
dead time.
Selects PWMxL3/PWMxH3 inactive edge
dead time.
DEAD-TIME ASSIGNMENT
DEAD-TIME RANGES
The user application should not modify the
PxDTCON1 or PxDTCON2 values while
the PWM module is operating (PTEN = 1).
Unexpected results can occur.
DEAD-TIME SELECTION BITS
Function
CY
, 2 T
CY
, 4 T
CY
or 8
Preliminary
14.10 Independent PWM Output
Independent PWM Output mode is required for driving
certain types of loads. A particular PWM output pair is
in the Independent Output mode when the correspond-
ing PMODx bit in the PWMxCON1 register is set. No
dead-time control is implemented between adjacent
PWM I/O pins when the module is operating in the
Independent PWM Output mode and both I/O pins are
allowed to be active simultaneously.
In the Independent PWM Output mode, each duty cycle
generator is connected to both of the PWM I/O pins in
an output pair. By using the associated Duty Cycle reg-
ister and the appropriate bits in the PxOVDCON regis-
ter, the programmer can select the following signal
output options for each PWM I/O pin operating in this
mode:
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
14.11 Single Pulse PWM Operation
The PWM module produces single pulse outputs when
the PxTCON control bits PTMOD<1:0> = 10. Only
edge-aligned outputs can be produced in the Single
Pulse mode. In Single Pulse mode, the PWM I/O pin(s)
are driven to the active state when the PTEN bit is set.
When a match with a Duty Cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PxTPER register occurs, the PxTMR
register is cleared, all active PWM I/O pins are driven
to the inactive state, the PTEN bit is cleared and an
interrupt is generated.
14.12 PWM Output Override
The PWM output override bits allow the user applica-
tion to manually drive the PWM I/O pins to specified
logic states, independent of the duty cycle comparison
units.
All control bits associated with the PWM output over-
ride function are contained in the PxOVDCON register.
The upper half of the PxOVDCON register contains
eight bits, POVDxH<4:1> and POVDxL<4:1>, that
determine which PWM I/O pins will be overridden. The
lower half of the PxOVDCON register contains eight
bits, POUTxH<4:1> and POUTxL<4:1>, that determine
the state of the PWM I/O pins when a particular output
is overridden via the POVD bits.
14.12.1
When a PWMxL pin is driven active via the PxOVD-
CON register, the output signal is forced to be the com-
plement of the corresponding PWMxH pin in the pair.
Dead-time insertion is still performed when PWM
channels are overridden manually.
COMPLEMENTARY OUTPUT MODE
© 2007 Microchip Technology Inc.