DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 174

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.7.2
When the CPU is placed in Idle mode and the QEI mod-
ule is configured in 16-bit Timer mode, the 16-bit timer
will operate if QEISIDL (QEICON<13>) = 0. This bit
defaults to a logic ‘0’ upon executing POR. To halt the
timer module during CPU Idle mode, QEISIDL should
be set to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally as if CPU Idle mode had not been entered.
15.8
The Quadrature Encoder Interface can generate an
interrupt on occurrence of the following events:
• 16-bit up/down position counter rollover/underflow
• Detection of qualified index pulse
• CNTERR bit is set
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF in the IFS3 register, is
asserted upon occurrence of any of these events. The
QEIIF bit must be cleared in software.
Enabling an interrupt is accomplished via the respec-
tive enable bit, QEIIE, in the IEC3 register.
DS70283B-page 172
Quadrature Encoder Interface
Interrupts
TIMER OPERATION DURING CPU
IDLE MODE
Preliminary
15.9
The QEI module has four user-accessible registers,
accessible in either Byte or Word mode:
• Control/Status Register (QEICON) – Allows con-
• Digital Filter Control Register (DFLTCON) –
• Position Count Register (POSCNT) – Allows
• Maximum Count Register (MAXCNT) – Holds a
trol of the QEI operation and status flags indicat-
ing the module state.
Allows control of the digital input filter operation.
reading and writing of the 16-bit position counter.
value that is compared to the POSCNT counter in
some operations.
Note:
Control and Status Registers
The
accesses,. However, reading the register
in Byte mode can result in partially
updated values in subsequent reads.
Either use Word mode reads/writes, or
ensure that the counter is not counting
during Byte operations.
POSCNT
© 2007 Microchip Technology Inc.
register
allows
byte