MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 106

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.16.2.2
This read/write register is used to control various optional features of the SCI system.
Note:
Freescale Semiconductor
Offset
93.
Reset
W
R
LOOPS
RSRC
Field
ILT
PE
(93)
PT
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
M
7
5
4
2
1
0
0x42
LOOPS
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the transmitter
output is internally connected to the receiver input.
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver
input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter
output.
9-Bit or 8-Bit Mode Select
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count
toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to
Wake-up” for more information.
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of
the data character (eighth or ninth data bit) is treated as the parity bit.
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s
in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including
the parity bit, is even.
SCI Control Register 1 (SCIC1)
7
0
0
1
RxD pin is not used by SCI.
0
1
0
1
0
1
0
1
0
1
Normal operation — RxD and TxD use separate pins.
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.)
Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
Normal — start + 8 data bits (LSB first) + stop.
Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB first) + 9th data bit + stop.
Idle character bit count starts after start bit.
Idle character bit count starts after stop bit.
No hardware parity generation or checking.
Parity enabled.
Even parity.
Odd parity.
6
0
0
Table 138. SCI Control Register 1 (SCIC1)
RSRC
Table 139. SCIC1 Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
M
4
0
Description
3
0
0
Serial Communication Interface (S08SCIV4)
ILT
2
0
Section 4.16.3.3.2.1, “Idle-line
PE
1
0
Access: User read/write
PT
0
0
106