MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 76

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.10
The MM912_634 analog die includes a configurable window watchdog, which is active in Normal mode. The
watchdog module is based on a separate clock source (f
D2DCLK clock. The watchdog timeout (t
Watchdog Register (WDR).
During Low Power mode, the watchdog feature is not active, a D2D read during Stop mode will have the WDOFF bit set.
To clear the watchdog counter, a alternating write must be performed to the Watchdog Service Register (WDSR). The first write
after the RESET_A has been released has to be 0xAA. The next one must be 0x55.
After the RESET_A has been released, there will be a standard (non-window) watchdog active with a fixed timeout of tIWDTO.
The Watchdog Window Open (WDWO) bit is set during that time and the window watchdog can be configured (WDR) without
changing the initial timeout, and can be trimmed using the trim value given in the MCU trimming Flash section. See
“MM912_634 - Analog Die
To enable the window watchdog, the initial counter reset has to be performed by writing 0xAA to the Watchdog Service Register
(WDSR) before tIWDTO is reached.
If the tIWDTO timeout is reached with no counter reset or a value different from 0xAA was written to the WDSR, a watchdog reset
will occur.
Once entering Window Watchdog mode, the first half of the time t
an alternating write of 0x55 and 0xAA must be performed within the second half of the t
indicate the current status of the window. A timeout or wrong value written to the WDSR will force a watchdog reset.
For debug purpose, the watchdog can be completely disabled by applying VTST to the TCLK pin while TEST_A is grounded.
The watchdog will be disabled as long as VTST is present. The watchdog is guaranteed functional for VTSTEN. The WDOFF bit
will indicate the watchdog being disabled. The WDSR register will reset to default once the watchdog is disabled. Once the
watchdog is re-enabled, the initial watchdog sequence has to be performed.
During Low Power mode, the Watchdog clock is halted and the Watchdog Service Register (WDSR) is reset to the default state.
4.10.1
4.10.1.1
Note:
Freescale Semiconductor
Offset
73.
Reset
W
R
(73)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
0x10
Window Watchdog
WDOFF
Register Definition
Watchdog Register (WDR)
7
0
Standard Initial Watch Dog (no window)
Trimming.
WDWO
6
0
Initial WD Reg.
WRITE = 0xAA
t
IWDTO
Figure 20. MM912_634 Analog Die Watchdog Operation
WDTO
Table 100. Watchdog Register (WDR)
MM912_634 Advance Information, Rev. 4.0
) can be configured between 10 ms and 1280 ms (typ.) using the
5
0
0
Window Watch Dog
Window Closed
t
WDTO
Window WD timing (t
/ 2
BASE
WRITE = 0x55
WD Register
4
0
0
) operating independent from the MCU based
Window Watch Dog
WDTO
Window Open
WDTO
t
WDTO
)
forbids a counter reset. To reset the watchdog counter,
/ 2
Window Watch Dog
Window Closed
3
0
0
WDTO
Window Watch Dog
2
0
. A Window Open (WDWO) flag will
Window Open
(to be continued)
WRITE = 0xAA
WD Register
WDTO
1
0
Access: User read/write
Window Watchdog
t
Section 4.26,
MCU
0
0
ANALOG
76