MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 310

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.40.4.3
Flash command operations are used to modify Flash memory contents.
The next sections describe:
4.40.4.3.1
Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide
BUSCLK down to a target FCLK of 1 MHz.
frequency.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not
been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded
during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set.
4.40.4.3.2
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous
command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register
are ignored.
4.40.4.3.2.1
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the
FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command
completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command
has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to
communicate any results. The flow for a generic command write sequence is shown in
Freescale Semiconductor
•
•
•
How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program
and erase command operations
The command write sequence used to set Flash command parameters and launch execution
Valid Flash commands available for execution
Flash Command Operations
Writing the FCLKDIV Register
Programming or erasing the Flash memory cannot be performed if the bus clock runs at less
than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress.
Setting FDIV too low can result in incomplete programming or erasure of the Flash memory
cells.
Command Write Sequence
Writes to any Flash register must be avoided while a Flash command is active (CCIF=0) to
prevent corruption of Flash register contents and Memory Controller behavior.
Define FCCOB Contents
Table 410
MM912_634 Advance Information, Rev. 4.0
shows recommended values for the FDIV field based on BUSCLK
CAUTION
NOTE
Figure
Section
114.
4.40.3.2.3).
Section
4.40.3.2.7) and
310