MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 288

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI data register is
not transmitted; instead the last received data is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK
cycle) between successive transmissions, then the content of the SPI data register is transmitted.
In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers
for at least minimum idle time.
4.39.4.3.3
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge
clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the n
transfer operation.
The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the
slave to transfer its first data bit to the serial data input pin of the master.
A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave.
When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI
shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin
of the master to the serial input pin on the slave.
This process continues for a total of n edges on the SCK line with data being latched on even numbered edges and shifting taking
place on odd numbered edges.
Note:
Freescale Semiconductor
200.
End of Idle State
n depends on the selected transfer width, please refer to
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
t
t
t
t
MOSI pin
MISO pin
L
T
I
L
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
, t
= Minimum idling time between transfers (minimum SS high time)
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
T
, and t
Figure 109. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width Selected (XFRW = 1)
I
CPHA = 1 Transfer Format
are guaranteed for the master mode and required for the slave mode.
MSB
LSB
t
L
1
2
Bit 14
Bit 1
3
4
Bit 13
Bit 2
5
Begin
6
Bit 12
Bit 3
7
MM912_634 Advance Information, Rev. 4.0
8
Bit 11
Bit 4
9
10
Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
Bit 5
11
12
Bit 6
13
Section 4.39.3.2.2, “SPI Control Register 2 (SPICR2)
14
Transfer
Bit 7 Bit 8 Bit 9 Bit 10 Bit 11Bit 12Bit 13Bit 14
15
16
17
18
19
20
Bit 5
21
22
Bit 4 Bit 3 Bit 2 Bit 1
23
24
25
End
26
27
28
29
30
MSB
LSB
31
32
t
T
Minimum 1/2 SCK
for t
Begin of Idle State
t
I
t
T
L
, t
l
, t
L
(200)
-cycle
288