MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 221

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.32.4.5.3
ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix refers to the tracing count.
The information format for Loop1 and Normal modes is identical. In Detail mode, the address and data for each entry are stored
on consecutive lines, thus the maximum number of entries is 32. In this case DBGCNT bits are incremented twice, once for the
address line and once for the data line, on each trace buffer entry. In Detail mode CINF comprises of R/W and size access
information (CRW and CSZ respectively).
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL) and the high byte is
cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte1 and the byte at the
higher address is stored to byte0.
4.32.4.5.3.1
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
Freescale Semiconductor
ADDR[17]
ADDR[16]
CRW
CSZ
Bit
Normal/Loop1
3
2
1
0
Detail Mode
Modes
Mode
Access Type Indicator — This bit indicates if the access was a byte or word size when tracing in Detail Mode
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access when
tracing in Detail Mode.
Address Bus bit 17 — Corresponds to system address bus bit 17.
Address Bus bit 16 — Corresponds to system address bus bit 16.
When tracing is terminated using forced breakpoints, latency in breakpoint generation
means that opcodes following the opcode causing the breakpoint can be stored to the trace
buffer. The number of opcodes is dependent on program flow. This can be avoided by using
tagged breakpoints.
Trace Buffer Organization (Normal, Loop1, Detail modes)
Information Bit Organization
0
1
0
1
Number
Entry 1
Entry 2
Entry 1
Entry 2
Word Access
Byte Access
Write Access
Read Access
Entry
Table 324. Trace Buffer Organization (Normal,Loop1,Detail modes)
CINF1,ADRH1
CINF2,ADRH2
Field 2
4-bits
PCH1
PCH2
0
0
Bit 3
CSZ
Table 325. Field2 Bits in Detail Mode
MM912_634 Advance Information, Rev. 4.0
Table 326. Field Descriptions
CRW
Bit 2
NOTE:
DATAH1
DATAH2
ADRM1
ADRM2
Field 1
PCM2
Description
8-bits
PCM1
ADDR[17]
Bit 1
ADDR[16]
Bit 0
DATAL1
DATAL2
ADRL1
ADRL2
Field 0
8-bits
PCL1
PCL2
221