MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 131

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.19.4.2
The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64, or 128. The prescaler select bits, PR[2:0], select the prescaler divisor.
PR[2:0] are in the timer system control register 2 (TSCR2).
4.19.4.3
Clearing the I/O (input/output) select bit, IOSn, configures channel n as an input capture channel. The input capture function
captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the
timer transfers the value in the timer counter into the timer channel registers, TCn.
The minimum pulse width for the input capture input is greater than two bus clocks.
An input capture on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests.
4.19.4.4
Setting the I/O select bit, IOSn, configures channel n as an output compare channel. The output compare function can generate
a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel
registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel n sets
the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests.
The output mode and level bits, OMn and OLn, select set, clear, toggle on output compare. Clearing both OMn and OLn
disconnects the pin from the output logic.
Freescale Semiconductor
PR[2:1:0]
Prescaler
Input Capture
Output Compare
16-BIT COMPARATOR
16-BIT COMPARATOR
EDG0A
TCNT(hi):TCNT(lo)
PRESCALER
16-BIT COUNTER
CHANNEL3
CHANNEL 0
TC0
TC3
EDG3A
EDG3B
EDG0B
D2D Clock
Figure 34. Detailed Timer Block Diagram
CLEAR COUNTER
DETECT
TE
DETECT
EDGE
EDGE
MM912_634 Advance Information, Rev. 4.0
C0F
C3F
OM:OL0
OM:OL3
TOV0
TOV3
TOF
TOI
IOC0
CxF
CxI
C0F
C3F
IOC3
INTERRUPT
LOGIC
IOC0 PIN
IOC3 PIN
LOGIC
LOGIC
Basic Timer Module - TIM (TIM16B4C)
channel 3 output
compare
TCRE
CH.3 COMPARE
CH. 0 COMPARE
CH. 0 CAPTURE
CH.3 CAPTURE
PA INPUT
IOC0 PIN
IOC3 PIN
TOF
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