MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 160

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.28.2.4
Note:
4.28.2.5
Note:
Freescale Semiconductor
147.
148.
Address 0x0002
Address 0x0003
Reset
Reset
DDRA
DDRA
Field
Field
W
W
R
7–4
3–0
R
PE
PE
1
0
Read: Anytime.
Read: Anytime.
Write: Anytime.
Write: Anytime.
Port E general purpose input/output data—Data Register, CPMU OSC XTAL signal
When not used with the alternative function, this pin can be used as general purpose I/O.
In general purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
Port E general purpose input/output data—Data Register, CPMU OSC EXTAL signal
When not used with the alternative function, this pin can be used as general purpose I/O.
In general purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
Port A Data Direction— This bit determines whether the associated pin is an input or output.
Port A Data Direction— This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to input or output. In this case the data direction bits
will not change.
• The CPMU OSC function takes precedence over the general purpose I/O function if enabled.
• The CPMU OSC function takes precedence over the general purpose I/O function if enabled.
DDRA7
1 Associated pin is configured as output.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port A Data Direction Register (DDRA)
Port E Data Direction Register (DDRE)
7
0
7
0
0
DDRA6
6
0
6
0
0
Figure 44. Port A Data Direction Register (DDRA)
Figure 45. Port E Data Direction Register (DDRE)
Table 230. PORTE Register Field Descriptions
Table 231. DDRA Register Field Descriptions
DDRA5
MM912_634 Advance Information, Rev. 4.0
5
0
5
0
0
DDRA4
4
0
4
0
0
Description
Description
DDRA3
3
0
3
0
0
DDRA2
Port Integration Module (S12IPIMV1)
2
0
2
0
0
Access: User read/write
Access: User read/write
DDRA1
DDRE1
1
0
1
0
DDRA0
DDRE0
0
0
0
0
(147)
(148)
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