C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 119

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

13. Prefetch Engine
The C8051F41x family of devices incorporate a 2-byte prefetch engine. Due to Flash access time specifi-
cations, the prefetch engine is necessary for full-speed (50 MHz) code execution. Instructions are read
from Flash memory two bytes at a time by the prefetch engine, and given to the CIP-51 processor core to
execute. When running linear code (code without any jumps or branches), the prefetch engine allows
instructions to be executed at full speed. When a code branch occurs, the processor may be stalled for up
to two clock cycles while the next set of code bytes is retrieved from Flash memory. The FLRT bit
(FLSCL.4) determines how many clock cycles are used to read each set of two code bytes from Flash.
When operating from a system clock of 25 MHz or less, the FLRT bit should be set to ‘0’ so that the
prefetch engine takes only one clock cycle for each read. When operating with a system clock of greater
than 25 MHz (up to 50 MHz), the FLRT bit should be set to ‘1’, so that each prefetch code read lasts for
two clock cycles.
Bits 7–6: Unused. Read = 00b; Write = Don’t Care
Bit 5:
Bits 4–1: Unused. Read = 0000b; Write = Don’t Care
Bit 0:
Note: The prefetch engine should be disabled when changes to FLRT are made. See
Bit7
R
PFEN: Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
FLBWE: Flash Block Write Enable.
This bit allows block writes to Flash memory from software.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of two.
“16. Flash Memory” on page 135
Bit6
SFR Definition 13.1. PFE0CN: Prefetch Engine Control
R
PFEN
R/W
Bit5
Bit4
R
.
Rev. 1.1
Bit3
R
Bit2
R
C8051F410/1/2/3
Bit1
R
SFR Address: 0xE3
FLBWE
R/W
Bit0
Section
00100000
Reset Value
119