C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 129

• Manufacturer Part Number: C8051F411-GMR
• Description: Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F411-GMR

• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 20 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Ram Size: 2.25 KB
• Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

15.2. Power-Fail Reset / V
When the VDD Monitor is selected as a reset source and a power-down transition or power irregularity
causes V
in a reset state (see Figure 15.2). When V
from the reset state. Note that even though internal data memory contents are not altered by the power-fail
reset, it is impossible to determine if V
flag reads ‘1’, the data may no longer be valid. The V
source after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset
source. For example, if the V
V
monitor must be enabled to the higher setting (VDMLVL = '1') and selected as a reset source if soft-
ware contains routines which erase or write Flash memory. If the V
erase or write performed on Flash memory will cause a Flash Error device reset.
The V
as a reset source before it is enabled and stabilized may cause a system reset. The procedure for re-
enabling the V
See Figure 15.2 for V
See Table 15.1 for complete electrical characteristics of the V
Note: Software should take care not to inadvertently disable the V
when writing to RSTSRC to enable other reset sources or to trigger a software reset. All writes to
RSTSRC should explicitly set PORSF to '1' to keep the V
DD
monitor will still be disabled after the reset. To protect the integrity of Flash contents, the V
DD
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
DD
monitor must be enabled before it is selected as a reset source. Selecting the V
to drop below V
DD
Note: This delay should be omitted if software contains routines which erase or
write Flash memory.
monitor and configuring the V
DD
monitor timing; note that the reset delay is not incurred after a V
RST
DD
DD
DD
DD
, the power supply monitor will drive the RST pin low and hold the CIP-51
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
monitor (VDMEN bit in VDM0CN = ‘1’).
monitor is disabled by software, and a software reset is performed, the
monitor to stabilize (approximately 5 µs). 
DD
DD
Monitor
dropped below the level required for data retention. If the PORSF
DD
returns to a level above V
DD
Rev. 1.1
monitor as a reset source is shown below:
DD
monitor is enabled and is selected as a reset
DD
DD
Monitor enabled as a reset source.
monitor.
C8051F410/1/2/3
DD
RST
DD
monitor is not enabled, any
, the CIP-51 will be released
Monitor as a reset source
DD
monitor reset.
DD
monitor
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DD