C8051F411-GMR Silicon Laboratories Inc, C8051F411-GMR Datasheet - Page 174
C8051F411-GMR
Manufacturer Part Number
C8051F411-GMR
Description
Microcontrollers (MCU) 50 MIPS 32KB 12ADC RTCLOCK 28 PIN MCU
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F410DK.pdf
(270 pages)
Specifications of C8051F411-GMR
Processor Series
C8051F4x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
20
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F410DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 20 Channel
On-chip Dac
12 bit, 2 Channel
Package
28QFN EP
Device Core
8051
Family Name
C8051F41x
Maximum Speed
50 MHz
Ram Size
2.25 KB
Operating Supply Voltage
1.8|2.5|3.3|5 V
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
Details
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C8051F410/1/2/3
19.4. System Clock Selection
The internal oscillator requires little start-up time and may be selected as the system clock immediately fol-
lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ-
ically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in
register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a
false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external
oscillator and checking XTLVLD. RC and C modes typically require no startup time.
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain peripherals (timers, PCA) when another oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscilla-
tor, smaRTClock oscillator, and Clock Multiplier, as long as the selected clock source is enabled and has
settled.
174
Bits7–6: Unused. Read = 00b; Write = don’t care.
Bits5–4: CLKDIV1–0: Output /SYSCLK Divide Value
Bit3:
Bit2:
Bits1–0: CLKSL1–0: System Clock Select
Bit7
R
-
These bits can be used to pre-divide the /SYSCLK output before it is sent to a port pin
through the Crossbar.
00: Output will be SYSCLK.
01: Output will be SYSCLK/2.
10: Output will be SYSCLK/4.
11: Output will be SYSCLK/8.
Unused. Read = 0b; Write = don’t care.
Reserved. Read = 0b; Must write 0b.
These bits select the system clock source.
Bit6
R
-
CLKSL
00
01
10
11
SFR Definition 19.5. CLKSEL: Clock Select
R/W
Bit5
CLKDIV
R/W
Bit4
Internal Oscillator (as determined by the
IFCN bits in register OSCICN)
Rev. 1.1
smaRTClock Oscillator
Bit3
External Oscillator
R
-
Selected Clock
Clock Multiplier
Reserved
R/W
Bit2
R/W
Bit1
CLKSL
SFR Address:
R/W
Bit0
0xA9
00000000
Reset Value
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